RTL Integration Engineer – PCIe Gen5 To Gen8

RTL Integration Engineer – PCIe Gen5 to Gen8.

Experience required: 8–12+ years in high-speed interface RTL integration.

Key skills:

PCIe Gen5+ controller and PHY integration, PCIe protocol layers (TL/DL/PHY), LTSSM, TLP/DLLP, flow control, replay, PIPE interface, multi-clock design, CDC, reset sequencing, and AXI/APB-based SoC integration.

Must have

silicon-proven PCIe Gen5+ experience; exposure to PCIe Gen6 FLIT-mode architecture is strongly preferred.
Preferred exposure: Chiplet/multi-die SoCs, CXL 2.x/3.x, retimer/redriver integration, post-silicon debug and bring-up, ASPM/low-power integration, RAS/AER, and IDE/link-level security.