RTL Lead – Physical AI Compute
You will lead RTL development for key portions of a Physical AI SoC. You will translate system requirements into microarchitectures, drive hardware/software co-design, make performance and power decisions, review RTL, establish engineering methodologies, and mentor RTL engineers.
Responsibilities
- Lead RTL development across key SoC components
- Translate system requirements into robust microarchitectures
- Drive hardware/software co-design across AI workloads, memory systems, runtime software, and system architecture
- Define programming models, execution flows, memory hierarchies, and performance-critical interfaces
- Drive design decisions across compute engines, memory subsystems, interconnect, control logic, and system infrastructure
- Conduct architecture and RTL reviews
- Establish engineering processes and design methodologies
- Mentor and develop RTL engineers
Requirements
- Strong RTL design experience in complex SoCs or related systems
- Deep understanding of digital design fundamentals and microarchitecture
- Experience with Verilog and SystemVerilog
- Familiarity with memory systems, interconnect fabrics, cache hierarchies, and system-level data movement
- Experience balancing performance, power, area, and design complexity
- Ability to drive technical projects from concept through silicon bring-up
- Experience with hardware/software co-design and system-level performance optimization
Benefits
- Performance-based incentives
- Equity participation
- Medical coverage
- Dental coverage
- Vision coverage
- Paid time off
- Flexible work arrangements