Senior ASIC Verification Engineer
Summary
Senior ASIC verification engineer writes and runs SystemVerilog/UVM testbenches to verify chip designs on-site in Tampere.
We are looking for a senior ASIC Verification with strong experience in SV and UVM.
Qualifications:
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8+ years of Industry Experience
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Deep Understanding of SystemVerilog and ASIC Verification in general
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Experience in formal verification methods and UVM
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Good team management and interpersonal skills
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Proficient in English.
Employees will be permanent with Swedium Global Services and will be working on-site at client location in Tampere.