Senior Backend Engineer - IC Design
Summary
Senior IC physical design (digital backend) engineer who takes chips from netlist to GDS — running place & route, static timing analysis, physical verification, and power analysis at block or top level using tools like Innovus/ICC2, PrimeTime, StarRC/QRC and Calibre, and debugging timing, SDC and UPF with front-end teams.
APR/STA senior engineers are responsible for completing the digital backend work from netlist to GDS, at the TOP or block level, including PR (place and route), STA (static timing analysis), PV (physical verification), PA (power analysis), and other tasks.
Key responsibilities
Complete digital backend work from netlist to GDS at TOP or block level
Perform PR (place and route), STA (static timing analysis), PV (physical verification), and PA (power analysis)
Collaborate with digital front-end engineers to debug issues such as timing, SDC, UPF.
Complete block level or TOP PD work with moderate difficulty or above pre/post mask eco
Collaborate with the design team to evaluate and optimize the digital area
Requirements
Microelectronics related major, bachelor's degree or above
More than 7 years of work experience
Familiar with the complete design process from Netlist to GDS
Proficient in using one or several sets of design tools related to Innovus/ICC2, PT/computers, lec/form, starrc/QRC, PTPX/volt, caliber
Experience in successfully tapping out chips with a process size below 14nm is preferred
Experience in working with low-power design chips is preferred
Experience in TOP P&R work is preferred (top level partition, bump assignment, RDL routing, ESD plan, feedthrough inserting, pin assignment)
Priority given to those with TOP STA experience
Equipped with PCIE, DDR and other high-speed interface P&R experience is preferred
Good English reading, writing, and communication skills
Possess innovative ability and team spirit
