Senior Design Verification (DV) Engineer
Summary
Leads end-to-end verification for IP, subsystems, and SoCs using SystemVerilog/UVM and modern DV methodologies, collaborating with design and architecture teams.
We are seeking an experienced Senior Design Verification (DV) Engineer with expertise in SoC/IP verification, SystemVerilog/UVM, and modern verification methodologies. The ideal candidate will lead end-to-end verification activities for IP, Subsystem, and SoC-level designs while collaborating with design, architecture, and cross-functional teams to achieve verification closure. Key Responsibilities Develop and execute verification plans for IP, Subsystem, and SoC-level designs. Verify SoCs with…