Senior Design Verification Engineer
Summary
Senior Design Verification Engineer (5-7 years) on the Data Center Connectivity DV team, building UVM testbenches from scratch for CPUSS/SoC verification, running functional and power-aware simulations, gate-level sims, and integrating VIPs for protocols like AXI, MAC and PHY at an optical semiconductor startup targeting AI infrastructure interconnects.
CScale is a startup backed by Sutter Hill Ventures and Atreides Capital - headquartered in Palo Alto, CA. Our executive team has a demonstrated track record of building and scaling category-defining semiconductor and infrastructure businesses at companies like Broadcom, Lumentum, Tesla, Apple, Samsung, Intel, and VMware.
CScale is developing next-generation optical semiconductor solutions for the AI infrastructure market, focused on enabling true “scale-up” architectures. Our mission is to replace traditional copper interconnects with advanced fiber-optic technologies that overcome the limitations of existing optics solutions and architectures.
We are seeking a Senior Design Verification Engineer (5–7 years of experience) to join our Data Center Connectivity DV team. This role is ideal for engineers passionate about building verification environments from the ground up, performing functional and power-aware simulations, and integrating VIPs for standard protocols such as MAC, PHY, and AXI. The position involves CPUSS integration, verification of cutting-edge technologies.
Key Responsibilities
- Take ownership oftest-bench development usingUVM for Subsystem and SoC.
- Translate test bench architecture specifications into detailed DV tasks and build verification environments from scratch.
- Develop key test bench components including agents, scoreboards for data integrity checks, pass/fail criteria, protocol assertions, and functional coverage points
- Set up UVM register model generation using register description files and industry-standard automation tools (e.g.,Autogen).
- Automate C-based register programming API generation from register description files through scripting.
- Perform complete address map and register verification using UVM Register methodology.
- Verify all features comprehensively, including standalone test cases, concurrent traffic, use-case scenarios, and corner cases.
- Debug regression failures, perform root cause analysis, and collaborate closely with designers to resolve issues
- Perform comprehensive power-aware verification across all voltage corners, validating power and sub-power domains along with retention strategies.
- Set up and execute gate-level simulations, including a dedicated test suite for GLS that covers system boot and main data-path functionality
Required Skills and Experience
- Education: B.E./B.Tech/M.E./M.Tech in Electrical, Electronics, or Computer Engineering.
- Experience: 5–7 years of strong hands-on DV development and integration experience in SoC, networking, or interconnect logic.
- Proficiency in System Verilog and UVM coding for verification. Knowledge of C language.
- Experience with ARM or RISC-V CPU subsystems.
- Solid understanding of connectivity and interconnect protocols such as AMBA (AXI/AHB/APB); familiarity with PCIe or Ethernet is a plus.
- Knowledge of clock/reset architectures, FIFOs, CDC, and low-power verification techniques.
- Strong debugging and problem-solving skills; experience with Git flow.
- Hands-on experience with simulation tools (e.g.,VCS, Questa).
- Strong knowledge of UPF (Unified Power Format), level shifter implementation, and power management strategies for low-power design.
Why This Role
- Work on next-gen data center connectivity.
- Gain deep exposure toDV architecture,UVM based TB development, E2E SoC development cycle and post-silicon bring-up.
- Be part of a highly technical team that values innovation, ownership, and learning.
- Competitive compensation, technical growth, and exposure to cutting-edge design challenges.
Skills
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