Senior Design Verification Engineer
Summary
Designs and verifies hardware-acceleration IP for AI/ML workloads using C++ and UVM testbenches.
Senior Design Verification Engineer
Location: Pune, Maharashtra, India
Workplace: on_site
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Follow →Designs and verifies hardware-acceleration IP for AI/ML workloads using C++ and UVM testbenches.
Location: Pune, Maharashtra, India
Workplace: on_site