Senior Design Verification Engineer (Unit Level Test)

The Role:
As a Design Verification Engineer, you will work with CPU designers, compiler team, performance team, and system verification team to generate the test cases automatically to fit those teams verification requirements in different perspectives. Your responsibilities will target establishing a highly scalable and reusable constrained random test bench that produces coverage driven tests.

Responsibilities:

• Review and influence product definition and specifications from a verification perspective and collaborate closely with the design team on feature specifications, test plans, and failure analysis.
• Develop checkers and assertions to verify the memory subsystem designs with interconnect.
• Develop tools, test benches, and test suites (UVM, C++/C, or otherwise as needed) to execute test plans.
• Develop and maintain an in-house Verification IP (VIP) tailored for memory subsystem and interconnect testing
• Write functional coverage, analyze both code and functional coverage, and close coverage holes.