Senior Digital Designer

About the Role
We are hiring a Senior Digital Designer to lead the RTL-to-tape-out design of digital blocks in our next generation of SoCs on the 28 nm, 40 nm, and 55 nm technology nodes. The role spans block-level architecture, RTL implementation, SoC-level integration and system validation, timing closure collaboration with the physical design team, silicon bring-up in the lab, and continued support through mass production. You will own critical blocks that combine mainstream cryptography accelerators with non-volatile memory interfacing — including QSPI controllers and Flash control state machines — and you will be a technical anchor for our digital design practice.

Key Responsibilities
● Own digital blocks end-to-end: specification, micro-architecture, RTL, synthesis, timing closure, and successful silicon.
● Drive SoC-level integration — assemble in-house blocks and third-party IP into the top-level, define bus / interconnect topology (AHB / AXI), clock and reset trees, pad ring, and power domains.
● Own SoC-level validation — build and extend system-level testbenches, run full-chip simulation across RTL and gate-level, validate boot sequences and firmware hooks, and drive sign-off coverage to closure.
● Design and integrate cryptography hardware — symmetric ciphers (AES), hash functions (SHA family), public-key algorithms (RSA, ECC), and TRNG blocks — meeting security, performance, and area targets.
● Design and integrate QSPI controllers and Flash control FSMs for on-chip and off-chip non-volatile memory — covering command sequencing (program / erase / read / status polling), timing budgets, boot-time initialization, and interaction with secure boot flows.
● Collaborate with verification, DFT, physical design, package, and CAD teams to close all sign-off criteria: functional, STA, power (IR/EM), DFT coverage, and physical verification.
● Lead silicon bring-up in the lab: debug functional and yield issues, define patches or ECOs, and drive corrections into mass-production releases.
● Interface with foundry and third-party IP vendors on process, integration, and errata questions.
● Mentor junior RTL engineers and contribute to internal design methodology, coding-style guidelines, and reusable design libraries.