Senior Digital IC Design Engineer-1 (LPDDR Integration Engineer)

【 Responsibilities 】

• LPDDR IP Integration
• SoC System Integration
• SoC performance emulation and optimization

【 Minimum Qualifications (Must Have) 】

• Education: Master’s degree or higher in Electrical Engineering, Electronics, Computer Engineering, or a related field.
• Work Experience: At least 2-5 years of experience in digital IC design.
• LPDDR/PCIE Integration: In-depth knowledge of LPDDR (4/4x/5/5x) protocols with hands-on experience in Controller /PHY integration and testing on FPGA platform.
• SoC Architecture & Integration: Proven experience in large-scale SoC development, including:

o Familiarity with AMBA (AXI/AHB) bus architectures, interrupt handling, and DMA mechanisms.
o Hands-on experience in Clock/Reset architecture planning and implementation (e.g., CDC/RDC handling).
o Deep understanding of System Boot Flow (from ROM/SRAM…etc to DRAM) and initialization sequences.

【 Preferred Qualifications (Nice to Have) 】

• Integration experience with high-speed peripheral interfaces such as MIPI or USB (3.2/4).
• Experience in troubleshooting high-speed Signal Integrity (SI) or Power Integrity (PI) issues.
• Background in FPGA Prototyping or Post-Silicon Debugging
• Expertise in Power Management strategy, including power domain partitioning, UPF/CPF flow, and low-power state control.
• Familiar with one of the following front-end EDA flows: Synthesis, STA, Lint/CDC, VCLP/Conformal LP, PTPX.