Position:

Senior Engineer (Level 1)

Job Description:

- Functional Area: RTL design, Lower Power Synthesis, Low Power Design, UPF Flow

- 5-20 years of experience in RTL design in Verilog, VHDL

- ASIC/FPGA experience

- If ASIC experience, then Lint/CDC tool experience

- If FPGA experience, then Xilinx or Altera/Intel FPGA parts and tools

- RTL debug experience

- Knowledge of at least one industry standard protocols like I2C/SPI/UART, PCIe, MIPI, AXI, Ethernet

Location:

IN-UP-Noida, India-World Trade Tower (eInfochips)

Time Type:

Full time

Job Category:

Engineering Services