Senior Engineer, Physical Design AI/ML

Job Title Senior Physical Design AI/ML Engineer, Logic Pathfinding Lab

What You’ll Do

We are looking for physical design engineers who have demonstrated skills in applying AI / Machine Learning tools in improving design simulation accuracy and throughput in predicting design performance, power, and area (PPA). Experience in optimization of design-technology co-optimization (DTCO) knobs in advanced logic nodes (2nm or beyond) is preferred.

The candidate will be a key technical member of the Logic Pathfinding Lab, part of the Samsung Semiconductor Inc (SSI) in San Jose. He or she will join a team of experts in researching and evaluating advanced technology options, and assisting in knowledge / technology transfer to the Samsung Logic Technology Development (TD) in Korea. The successful candidate will be responsible for researching and evaluating new device architectures, materials, and integration schemes through chip design metrics to meet the need of sub-2nm technology nodes. The candidate should have demonstrated skills and experience in standard cell architecture creation, logic cell library characterizations Place and Route, Process Design Kit (PDK) generation, and a strong understanding of Logic process integration. The candidate should have excellent communication skills, and be able to collaborate with and guide multiple organizations, including research consortia.

Location: Daily onsite presence at our San Jose office/headquarters in alignment with our Flexible Work policy

Reports to: Sr Director

Direct Reports: N/A

• Design, build, and implement machine learning and generative models to optimize chip layout designs to maximize performance, power, and area (PPA) efficiency, while using explicit domain knowledge of hardware design rules and constraints
• Automate and accelerate Design Implementation steps such as Floor-planning, Placement and Routing, Clock Tree Synthesis, using exploratory PDKs developed by the team
• Automate and accelerate Verification steps such as Design Rule Checks (DRC) and Layout versus Schematic (LVS) Checks using exploratory PDKs developed by the team
• Collaborate with other team members to automate all aspects of exploratory PDK generation, including developing automated QA systems
• Applying machine learning techniques to extract and develop correlations among data in different domains, e.g. device, RO benchmark circuits, larger circuit blocks, at different operating conditions
• Develop internal benchmarking capability based on available data, modeling, or learning from multiple sources, and create assessments to share with internal R&D team
• Complete other responsibilities as assigned.

What You Bring

• PhD with industry experience preferred
• RTL synthesis, place and route, and timing analysis skills
• Understanding of clock and power delivery network schemes
• Hands-on experience on machine learning or deep learning projects for scientific and/or engineering applications, e.g., regression, surrogate modeling, inverse design, graph neural networks
• Strong Python and/or C++ skills, including expertise in machine learning packages like PyTorch and Tensorflow
• Experience in using Bayesian optimization and/or active learning frameworks for design space exploration
• Expertise with agentic AI frameworks (LangGraph, CrewAI, ADK)
• You’re inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

Preferred qualifications

• Familiarity with state-of-the-art AI workloads and their compute and memory requirements
• Experience with setting up and optimization of a local, private, compute cluster to run latest LLM models
• Proficiency in EDA tools for synthesis and layout
• Prior experience using generative AI for chip design/optimization

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