Senior Front-End ASIC RTL/Logic Design Engineer - Lead
Summary
Leads the design of high-speed digital ASIC architectures, writing RTL in HDL, and collaborating with verification and back-end teams to ensure silicon success and debug support.
754 Altera Semiconductor Technology (M) Sdn. Bhd. is seeking a skilled individual to lead and define the design of high-speed digital architecture. The role involves close collaboration with verification and back-end teams, ensuring successful implementation and support for post-Silicon debug.
The ideal candidate will have at least 10 years of experience in ASIC frontend design and must possess strong communication and leadership skills, as well as proficiency in RTL coding using HDL languages. This role is based in Penang, Malaysia.