Senior Layout Engineer

This is a permanent position attached to a Company which develops chips for Data Processing, IP Licensing, Network, Bus, Chiplet Interconnect as well as Chip Customization for different customers

Location: North East

Job Scope

-Realize layout design from schematic presentation.

-Layout design implementation includes the following functions:

-Floor planning and device placement

-Power and Signal routings and Integrity optimization

-DRC/LVS/ERC/ANT/ESD/PERC/LVL and necessary Physical Verification

-Passing DRC rules and ensuring LVS

-Preparing material and reviewing of layout

-Checklist/Methodology to ensure quality of layout

-Layout methodology and enhancement

-Participate in post layout adjustments and block/IP activities

-Mentoring of junior layout engineers

-Participate in development of layout best practices and methodology

Requirements

-Diploma or Bachelor’s in Electrical/Computer/Electronics Engineering or equivalent.

-Good understanding of AMS layout fundamentals/EMIR/RC delay/Decoupling Caps/Latch-up

-Experience working on technology node below 16nm

-Experience working on high-speed or RF layout.

-Experience in TX/RX/PLL/ADC/DAC/etc. is a plus.

-Experience working with Cadence skills or equivalent tools for pcell development (perl/python/tcl) and automation to increase layout productivity.

-Hands-on working experience in layout engineering.

-Experience working with leading industry CAD tools, methodology and finfet technology.

-Experience with analog/digital on top (chip-top) integration is a plus point.

-Understanding of process technology and circuit design.

-Understanding of analog layout physical verification CAD setup.

Work Hours

Monday to Friday 9am to 6pm, 5 day week

To Apply

WhatsApp resume: 8023 1992 or

Email resume: [email protected]