Senior Physical Design EMIR Engineer, Google Cloud

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will be part of a team developing System on a Chips (SoCs) used to accelerate machine learning computation in data centers. You will collaborate with members of architecture, verification, power and performance, physical design etc. to specify and deliver high quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

• Define and drive to the implementation of physical design European Market Infrastructure Regulation (EMIR) methodologies.
• Take ownership of EMIR of one or more physical design partitions or top level.
• Drive to the closure of EMIR a of the SoC design.
• Contribute to design methodology, libraries, and code review.
• Define the physical design related rule sets for the functional design engineers.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience with advanced design, including clock/voltage domain crossing, Design for Testing (DFT), and low power designs.
• Experience with EMIR convergence on blocks/Sub-System (SS)/SoC.
• Experience in automation and scripting with TCL/Python.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience in coding with System Verilog and scripting with TCL.
• Experience with Very Large Scale Integration (VLSI) design in SoC or multiple-cycles of SoC in Application-Specific Integrated Circuit (ASIC) design.
• Experience with layout verification and design rules.