Senior Physical Design Engineer

You will execute the physical implementation of high-speed PCIe IP and sub-systems for an AI chip. You will own the full physical design flow from netlist to GDSII, working closely with circuit design, DFT, and verification teams to deliver silicon-proven, high-performance designs on leading-edge process nodes. You will handle floorplanning, placement, clock tree synthesis, routing, timing analysis, and physical verification signoff, while also contributing to internal methodology and flow automation.

Responsibilities

• Own end-to-end physical design flow: floorplanning, placement, CTS, routing, STA, physical verification and signoff for PCIe controller and PHY blocks
• Perform timing closure for high-speed PCIe Gen 4/5/6 interfaces across PVT corners
• Drive power integrity analysis including IR drop and electromigration (EM) across the power delivery network
• Achieve physical verification closure including DRC, LVS, and ERC signoff using Calibre tool
• Work with RTL and synthesis teams to provide feedback on logic restructuring for timing and area improvement
• Contribute to internal PD methodology, scripts, and flow automation using Perl and Tcl
• Support tapeout activities including final GDS merge, fill insertion, and signoff checks

Requirements

• B.S. / M.S. in Electrical Engineering, Computer Engineering, or related field
• 5+ years of hands-on physical design experience in advanced TSMC process nodes (N6 and below preferred)
• Strong knowledge of PCIe protocol and high-speed interface physical design constraints
• Strong hands-on experience with CTS for high-speed designs: CTS strategies, skew balancing, useful skew and multi-corner CTS closure
• Hands-on proficiency with industry-standard PnR and timing signoff tools (Cadence Innovus / Synopsys Primetime / Tweaker)
• Experience in resolving chip level DRC / LVS / EMIR issues for advance nodes
• Experience in multi-die packaging (WoW, 2.5D / 3D), Thermal / IR / EM signoff, signal integrity, or DFT-aware physical design is a plus
• Proficiency using Python, Perl, Tcl, Make scripting is a plus
• Tape out experience required

Benefits

• Attractive welfare benefits and developmental opportunities such as training and mentoring