Senior/Principal Photonic-Electronic Co-Design & Packaging Engineer_ Silicon Photonic(Taipei)

Position Overview
We are seeking a highly versatile and cross-disciplinary engineer to lead the chip level integration of complex photonic-electronic systems. This role spans front-end, back-end implementation, and advanced packaging of EIC and PIC. The ideal candidate will architect robust and scalable multi-chip systems while collaborating closely with optics and electrical teams on system-level integration.

Key Responsibilities

• Multi-Domain Co-Design & Architecture: Lead chip-to-chip packaging architecture for high-I/O systems (500–10,000+ channels), integrating photonic and electronic dies.
• Layout Strategy: Work with design teams to define and optimize layout strategies and high-speed electrical interconnects.
• Advanced Packaging Development: Design and implement high-density interconnect solutions using TSV, TMV, hybrid bonding, and silicon/glass interposers.
• Cross-Functional Integration: Collaborate with photonics teams on waveguide layout and interface with electronics teams on system-level integration and specifications.
• Supplier Engagement: Qualify and manage OSAT and foundry partners for assembly and testing, leading DFM/DFT initiatives.

Qualifications

• PhD/MSc in Electrical Engineering, Materials Science, Photonics, or a related field.
• 3+ years of experience in multi-chip packaging or complex system co-design.
• Proven background in high-density interconnect design (≥500 I/O, 2.5D/3D integration).
• Background knowledge of Si photonics is preferred.