Senior/Staff Front-End Engineer (SOC)

You will implement Verilog RTL for various sections of an SoC, working closely with IP engineers to integrate IPs into the overall design. You'll support synthesis, timing closure, power reduction, and floorplanning efforts aimed at optimizing performance and efficiency. You will also contribute to design verification and emulation, helping debug issues that arise across both pre-silicon and post-silicon stages.

Responsibilities

• Implement Verilog RTL for various sections of SoC
• Work with IP engineers to integrate IPs to the SoC
• Support synthesis, timing closure, power reduction, and floorplanning efforts to optimize performance and efficiency
• Contribute to design verification & emulation and assist in debugging issues across pre-silicon and post-silicon stages

Requirements

• Master's degree (preferred) or Bachelor's degree in Electrical Engineering or Computer Engineering with 5 years or more in a semiconductor or high technology R&D experience would be appreciated
• Verilog RTL development experience with industry-standard tools in an SoC environment
• Strong understanding of SoC architecture and logic design
• Strong problem-solving and debugging skills
• Knowledge of clocking, reset sequences, power-up sequences, and power management
• Exposure to verification methods
• Comfort with scripting languages (Perl, Shell, TCL) to automate design tasks
• Knowledge of emulation and FPGA prototyping is preferred