Senior System Validation Engineer(台北)

Senior System Validation Engineer

FPGA / ASIC | PCIe / NVMe

工作內容

【Job Responsibilities】

Lead FPGA prototype and ASIC post-silicon bring-up, host system integration, and system-level validation in Linux environments.

Develop and execute validation plans covering PCIe / NVMe functionality, data integrity, performance, stability, stress testing, error recovery, and host compatibility / interoperability.

Develop and maintain host-side test tools using C/C++, Python, and Shell Script to support automated testing, regression testing, and test result analysis.

Debug and analyze system-level integration issues across FPGA / ASIC, firmware, drivers, and Linux host environments; identify root causes and collaborate with engineering teams on issue resolution.

Collaborate with ASIC, firmware, software, and other engineering teams to resolve cross-functional system integration and validation issues.

Support PCIe / NVMe compliance and conformance testing, analyze test failures, and work with design teams to improve product quality.

Establish and maintain host compatibility matrices covering host platforms, CPUs, BIOS, OS / kernel, and driver versions. Manage validation plans, test records, issue tracking, validation reports, and release readiness.

【工作內容】

負責 FPGA Prototype 與 ASIC Post-Silicon 的 Bring-up、Linux Host System Integration 及系統層級驗證。

規劃並執行 PCIe / NVMe 功能、資料完整性、效能、穩定性、壓力測試、錯誤復原，以及 Host Compatibility / Interoperability 等驗證項目。

使用 C/C++、Python 與 Shell Script 開發及維護 Host-side Test Tools，執行自動化測試、Regression Testing 與測試結果分析。

分析與除錯跨 FPGA / ASIC、Firmware、Driver 及 Linux Host 的系統整合問題，定位 Root Cause，並與工程團隊合作解決。

與 ASIC、Firmware、Software 及其他工程團隊合作，處理跨部門系統整合及驗證問題。

協助 PCIe / NVMe Compliance / Conformance 測試，分析測試失敗原因，並與設計團隊合作改善產品品質。

建立與維護 Host Compatibility Matrix，涵蓋 Host Platform、CPU、BIOS、OS / Kernel 及 Driver 版本，並管理 Test Plan、測試紀錄、Issue Tracking、Validation Report 與 Release Readiness。