數位IC驗證副理/經理(馬來西亞)

1. Lead the development of UVM-based testbenches for block-level and system-level verification.
2. Define verification plans based on design specifications and functional requirements.
3. Develop reusable verification components such as drivers, monitors, scoreboards, and agents.
4. Implement constrained-random, directed, and coverage-driven test scenarios.
5. Analyze functional coverage and code coverage metrics; drive closure of coverage gaps.
6. Integrate and verify third-party IPs and interface protocols (e.g., RISCV, AMBA, ISP, MIPI, etc. )
7. Mentor and guide junior verification engineers in UVM methodology and best practices.
8. Collaborate with cross-functional teams to review specifications, participate in design and verification reviews, and contribute to continuous process improvement.
9. Document verification environments, test plans, and results for project tracking and future reuse.