Silicon Photonics Tape-out & Foundry Integration Engineer

About ATI

Accelight Technologies (ATI) is a global optical connectivity company developing and manufacturing high-speed optical solutions for AI infrastructure, hyperscale data centers and telecommunications networks.

Founded in 2017, ATI has grown rapidly alongside the increasing demand for high-speed optical connectivity. Our technology portfolio spans high-speed optical transceivers, silicon photonics, passive optical products and next-generation optical interconnect technologies.

ATI operates R&D centers in Wuhan Optics Valley and Silicon Valley, with manufacturing operations in China and Thailand. We are now expanding our global R&D footprint with the establishment of a new R&D team in Singapore, focused on advanced optical technologies and next-generation connectivity solutions.

As AI and high-performance computing continue to drive unprecedented demand for bandwidth, ATI is investing in advanced technologies including 1.6T and beyond, silicon photonics and next-generation optical interconnect architectures. We are building a global team of engineers and technology specialists to help develop the optical infrastructure that will support the next generation of computing.

Core Responsibilities

Responsible for managing the technical interface between silicon photonics chip design and wafer fabrication, including foundry PDK integration, tape-out readiness and verification, foundry coordination, wafer fabrication follow-up, yield analysis, failure analysis, and process improvement.

PDK Management & Foundry Process Interface

Review and evaluate silicon photonics Process Design Kits (PDKs) provided by wafer foundries and integrate them into internal EDA design flow. Support the design team in understanding foundry design rules, device models and process limitations. Work with foundry partners on custom device requirements, PDK enhancements and process optimization where required by product specifications.

Tape-out Readiness & Layout Verification

Own final tape-out readiness review for silicon photonic integrated circuits (PICs), including layout compliance, Design-Rule-Check/Layout-Versus-Schematic (DRC/LVS) and other foundry-required verification checks. Coordinate resolution of layout and verification issues with the design team and foundry to ensure complete and compliant tape-out submission.

Foundry Coordination

Serve as the primary technical interface with wafer foundries throughout the tape-out and fabrication process. Coordinate tape-out schedules, submission requirements, foundry technical queries and fabrication status, and drive timely resolution of process or manufacturing issues.

Yield Analysis, Characterization & Failure Analysis

Track wafer fabrication status and review WAT (Wafer Acceptance Test) and post-fabrication characterization data. Analyze wafer- and die-level performance and yield, identify process-related performance variations and yield-limiting factors, and work with foundry partners and internal design/test teams on failure analysis and corrective actions. Drive process and design improvements to enhance yield, performance and manufacturing robustness.

Education: Bachelor’s degree in Physics, Microelectronics, Semiconductor Engineering, Electrical/Electronic Engineering, or a related discipline. A Master’s or PhD in a relevant field is advantageous.

EDA Tools: Proficiency with relevant photonic and semiconductor EDA tools and tape-out verification flows. Experience with tools such as Ansys Lumerical, Luceda IPKISS, Cadence, Synopsys Opto Designer and Siemens Calibre is preferred. Strong hands-on experience with DRC/LVS and foundry tape-out verification is highly desirable.

Technical Knowledge: Strong understanding of silicon photonics fabrication processes, PIC layout and tape-out flows, foundry design rules, process variation, wafer-level characterization and semiconductor yield analysis.

Relevant Experience: Minimum 2 years of relevant experience in silicon photonics PIC tape-out, foundry process integration, yield improvement, or related semiconductor manufacturing activities. Candidates with 5+ years of directly relevant experience are preferred.