SoC Physical Design Engineer — Power, P&R & Timing in , United States
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Nokia is seeking an experienced ASIC physical design engineer to contribute to next- Optical Network ASICs. You will learn and apply advanced node flows, developing efficient implementation flows to optimize power, performance, and area.
You will collaborate with design and hardware teams, perform timing closure, and drive technology evaluations across 3/5/7nm nodes. A strong scripting background and hands-on P&R experience are essential for success.
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