SoC Power Engineer, Annapurna Labs - Cloud Scale Machine Learning
Summary
Develops power models and analyses for AI accelerators (Inferentia/Trainium SoCs) across design stages, collaborating with architects, designers, and engineers to optimize power efficiency and validate simulations with lab measurements.
Our Machine Learning Acceleration (MLA) team develops the Inferentia and Trainium SoCs that are used to power today’s AI workloads in datacenters all around the world. As a SoC Power Engineer, you’ll contribute to the project at the ground level by modeling and estimating power at every stage of the design from early RTL to final netlist and by driving ways to reduce power consumption of our machine learning accelerators.
We’re searching for an experienced SoC Power engineer with a background in Power analysis with a proven track record of handling challenges at scale. In this role, you’ll be working directly with architects, designers, verification engineers, software teams, and Physical Design experts - defining best practices to reduce power and model power consumption with high accuracy.
Key job responsibilities
* Responsible for full chip power analysis & modelling at various stages of design (RTL to gate level netlist)
* Develop and maintain dashboards for power rollups
* Work with designers, architects, Verification engineers and Physical Design engineers to develop vectors for IR analysis, Thermal analysis and power estimation
* Give feedback to designers and architects on how to reduce power
* Make power measurements in the lab and correlate back to simulations.
* Work with Emulation engineers to model chip-level power consumption
We’re searching for an experienced SoC Power engineer with a background in Power analysis with a proven track record of handling challenges at scale. In this role, you’ll be working directly with architects, designers, verification engineers, software teams, and Physical Design experts - defining best practices to reduce power and model power consumption with high accuracy.
Key job responsibilities
* Responsible for full chip power analysis & modelling at various stages of design (RTL to gate level netlist)
* Develop and maintain dashboards for power rollups
* Work with designers, architects, Verification engineers and Physical Design engineers to develop vectors for IR analysis, Thermal analysis and power estimation
* Give feedback to designers and architects on how to reduce power
* Make power measurements in the lab and correlate back to simulations.
* Work with Emulation engineers to model chip-level power consumption