Sr. ASIC Design Engineer(台北)

1. Architect a block of an ASIC and write a microarchitecture specification (MAS) for the block
2. Collaborate with other team members to integrate the block with the full chip
3. Use Verilog to design and System Verilog for block level verification
4. Assist the Verification team in reviewing and debugging test cases
5. Run LINT and CDC checks on the RTL code and fix accordingly.
6. Assist with synthesis and FPGA emulation.