Sr. High speed analog design engineer-Communication mixed signal(台北)

1. 5+ years experiences with MS in EE
2. Hands on experiences on the design and validation of wireline high speed silicon
3. Experiences with strong design capability for the 10Gbps+ wireline data transfer
4. Experience with USB 3.1, or PCIe 3.0 and PCIe 4.0 is a plus