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Sr. Physical Design CAD Engineer

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Summary

Senior engineer on AMD's Silicon CAD team building and maintaining physical design CAD flows and automation for next-gen CPU, GPU, APU, AI, and SoC chips. Day-to-day involves EDA tool deployment and qualification (Synopsys Fusion Compiler, IC Compiler II, PrimeTime), PPA debugging, regression infrastructure, and TCL/Python automation; hybrid role in Austin, TX.



ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.




THE ROLE:

This is a great opportunity to develop and maintain world-class hardware physical design flow in a fast-paced production environment on the very edge of modern technology! The goal of our Silicon CAD team at AMD is to determine a set of standards and techniques for designing chips with the highest performance, lowest cost, and lowest power usage. We then automate these best practices into a software design flow for efficiency and consistency, and work with various design teams to put the software to use in constructing next-generation GPUs, CPUs and APUs with industry-standard EDA software tools such as Synopsys IC Compiler II, Fusion Compiler and Primetime.

THE PERSON:

You are a highly motivated self-starter with a passion for solving complex engineering challenges and driving practical solutions. You thrive in fast-paced environments, work effectively with minimal supervision, and demonstrate strong ownership from problem identification through implementation.

You possess excellent troubleshooting, communication, and collaboration skills and enjoy working across multiple engineering organizations. You are comfortable operating in a highly visible central engineering team and can effectively partner with both internal design groups and external EDA vendors to deliver impactful results.

KEY RESPONSIBILITIES:

  • Develop, maintain, and enhance Physical Design CAD flows supporting AMD's AI, HPC, CPU, GPU, and SoC programs.
  • Deploy and support industry-standard EDA tools and methodologies across multiple design projects.
  • Develop innovative Physical Design solutions for place-and-route, timing closure, power optimization, and design convergence.
  • Debug and optimize physical design challenges related to power, performance, and area (PPA).
  • Create and maintain validation environments, test suites, regression infrastructure, and qualification methodologies.
  • Evaluate, qualify, and integrate new EDA tool capabilities and vendor technologies.
  • Collaborate closely with design teams to improve methodology efficiency, scalability, and productivity.
  • Work directly with EDA vendors, including Synopsys and Cadence, to drive tool enhancements and future roadmap requirements.
  • Improve and maintain CAD infrastructure, automation frameworks, and engineering workflows.
  • Leverage AI technologies, automation, and intelligent workflows to improve productivity, reduce design cycle time, and increase engineering efficiency.
  • Provide technical guidance, customer support, and methodology expertise to engineering teams worldwide.

PREFERRED EXPERIENCE:

  • Strong experience with Physical Design implementation and CAD flow development.
  • Hands-on expertise with Synopsys Fusion Compiler, Cadence Innovus, and PrimeTime.
  • Experience with physical verification, extraction tools (StarRC or equivalent), and timing signoff. Deep understanding of power, performance, and area (PPA) optimization.
  • Strong TCL and Python scripting skills for automation and tool development.
  • Experience supporting multiple chip tape outs and production design environments.
  • Ability to debug and solve complex Physical Design flow and methodology issues.
  • Experience working directly with EDA vendors such as Synopsys or Cadence.
  • Demonstrated use of AI tools or automation to improve engineering productivity.
  • Strong communication, collaboration, and problem-solving skills.

ACADEMIC CREDENTIALS:

  • Bachelor’s or master’s degree in electrical engineering, Computer Science, or equivalent is preferred

This role is not eligible for visa sponsorship.

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

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