Sr. Staff Engineer, Hardware and Silicon Validation
Posted Updated
Description
- Complete responsibility for PCIe/Ethernet PHY Validation in a post-silicon environment. Defining, documenting, executing, and reporting the overall PHY validation/test plan for Marvell's in-house IP.
- Lab-based silicon bring-up and unit test execution focused on PCIe/Ethernet Physical & PCS layer hardware and firmware functionality, while also extending to the protocol layer of the PCIe stack.
- Perform high-speed signal validation and analysis using various test equipment to measure Eye diagram/Jitter/BER. Analyze and debug issues on Phy protocol of storage interfaces (PCIe, Ethernet, etc.).
- Troubleshoot failing tests with diagnostics, software tools, hardware analyzers, oscilloscopes, meters, and logic/protocol analyzers. Lead collaborative technical discussions to drive resolution on technical issues.
- Work with cross-functional teams and external vendors to debug any post-silicon and/or customer issues related to PCIe/Ethernet PHY. Work closely with customers to address design issue and debug failure cases.