STA / Synthesis Engineer (Staff / Senior Staff / Principal)

You will own RTL-to-gate synthesis, static timing analysis, timing closure, power optimization, and sign-off readiness for complex AI and high-performance computing silicon. You will develop timing constraints, optimize low-power implementations, execute ECOs, automate flows with scripts, and collaborate with engineering functions to resolve implementation issues and improve methodology.

Responsibilities

• Drive RTL-to-gate synthesis for complex compute, CPU, VPU, AI accelerator, and low-power cores.
• Own synthesis setup, constraints, optimization, quality checks, and netlist delivery.
• Lead static timing analysis and timing closure across modes, corners, voltage domains, and clock domains.
• Optimize designs for timing, power, area, and cost.
• Develop, validate, and maintain timing constraints.
• Drive multi-mode multi-corner timing analysis, constraint management, timing debug, and convergence.
• Resolve timing, constraint, clocking, reset, DFT, and low-power implementation issues with partner functions.
• Own timing sign-off readiness and compliance with timing, power, signal integrity, and implementation-quality requirements.
• Drive hierarchical timing closure across blocks, subsystems, and full-chip interfaces.
• Implement low-power design strategies including clock gating, multi-voltage domains, power-aware synthesis, and UPF/CPF power-intent flows.
• Execute timing ECO flows for design closure.
• Support physical-aware synthesis and placement-aware optimization.
• Define and improve synthesis, STA, constraint, ECO, and timing-closure methodologies.
• Evaluate and deploy EDA tools, flows, and automation.
• Develop Tcl, Perl, or Python scripts to automate synthesis, STA, reporting, debug, and flow validation.
• Provide technical leadership in implementation, timing closure, and sign-off quality.

Requirements

• 5–15 years of hands-on experience in ASIC/SoC implementation, synthesis, STA, and timing closure.
• Experience with RTL-to-gate synthesis and timing closure for complex digital designs.
• Experience with compute, CPU, VPU, AI accelerator, SoC, or high-performance digital IP designs.
• Expertise with Synopsys and Cadence synthesis and STA tools.
• Understanding of multi-mode multi-corner timing analysis, constraint development, timing debug, and sign-off methodology.
• Experience with hierarchical, block-level, subsystem-level, and full-chip timing closure.
• Experience with advanced process technologies, including 2nm or 3nm nodes.
• Understanding of low-power design, multi-clock domains, clock gating, multi-voltage domains, and power-aware implementation.
• Experience with UPF/CPF power intent, isolation, level shifters, retention, and low-power timing closure.
• Experience with ECO flows and sign-off closure.
• Tcl, Perl, or Python scripting skills for synthesis and STA automation.

Benefits

• Performance-based incentives
• Equity participation
• Medical coverage
• Dental coverage
• Vision coverage
• Paid time off
• Flexible work arrangements