Staff Engineer (IC Design)
Summary
Staff-level digital IC design engineer in Singapore doing middle-end implementation: creating gate-level netlists, writing SDC/UPF constraints, running formal equivalence checks and STA, and validating ECOs using Synopsys/Cadence EDA tools. Requires 5+ years of digital IC design experience.
Key Responsibilities:
- Perform middle-end IC design tasks:
- Create optimized gate-level netlists
- Develop and validate SDC constraints
- Support DFT and power intent (UPF)
- Perform formal equivalence checks and Static Timing Analysis (STA)
- Assist with floorplanning and clock tree design
- Implement and validate ECOs
- Improve IC design flows and methodologies.
- Take on tasks as assigned to support smooth business operations.
- Adapt to changes as the business evolves.
Requirements:
- Bachelor’s or Master’s degree in Electrical/Electronic Engineering
- 5+ years of experience in digital IC design
- Skilled with EDA tools (e.g. Synopsys, Cadence)
- Experience with graphics processors or microcontrollers is a plus
If interested, please submit your application with your expected salary and resume.
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JDA WMS Pte Ltd | EA Personnel: Pham Thi Tuyet Mai
EA License No: 23S1595 | EA Registration No: R25127838