Staff Power Integrity Engineer, Seoul, Korea
About
We are seeking a highly skilled Senior or Staff Power Integrity Engineer to lead the design, simulation, and validation of advanced Power Delivery Networks (PDNs) for our next-generation AI chips, packages and systems for Tesla's Robotaxi, Optimus and data center. This critical role owns the integrity of high-current power delivery from the voltage regulator output down to the SoC, ensuring minimal noise, and superior power efficiency.
Responsibilities
• Architect and optimize low-impedance PDNs, including VRMs, PCB planes, and pcb/package-level decoupling strategies, to meet strict target impedance and voltage droop specifications
• Perform 3D/2D electromagnetic simulation, DC IR drop, AC impedance, and transient analysis using industry-standard tools (Ansys SIwave/HFSS, Cadence Sigrity/PowerSI)
• Collaborate closely with SoC design, package, and PCB layout teams to influence stack-up, ballmaps, and routing guidelines to achieve first-pass silicon success
• Define PI test patterns and validation items; lead lab bring-up, measurement, and debugging of PI issues; correlate simulation models with measurements using VNAs, Oscilloscopes
• Develop and standardize automated simulation workflows and reporting pipelines (Python, MATLAB, or TCL)
• Act as the design owner, mentor junior engineers, and drive technical decisions across cross-functional teams
Requirements
• 5+ years of relevant industry experience in Power Integrity, Power Delivery Network (PDN) design, or related field
• Deep understanding of EM theory, transmission line theory, and DC/AC circuit analysis
• Proficient in EDA tools such as Ansys (HFSS, SIwave, Q3D), Cadence (Sigrity PowerSI/PowerDC), or Keysight ADS
• Hands-on experience with high-speed instruments such as VNA, Oscilloscopes, or TDR
• Degree in Engineering, Computer Science, or equivalent in experience and evidence of exceptional ability
Preferred
• Background in advanced IC packaging technologies (including 2.5D/3D integration, silicon interposers, and chiplets), on-chip IR analysis, signal integrity preferred
Benefits
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