Staff Silicon Architect, DeepMind
Summary
Design and implement novel hardware accelerators for AI workloads, codesigning systems with software and algorithms to optimize performance and efficiency in Google’s data centers.
As a part of today's hyperscale AI competition, accelerators have become a strategic differentiator. In this role, you will help deliver codesigned systems that, unlike classic data center infrastructure, must meet future demands as our workloads continue to evolve and mutate. You will deploying new hardware in Google data centers through our projects to drive enhanced capabilities and efficiency, partner closely with the teams responsible for Google’s technical infrastructure to successfully deliver these systems.
We are pushing the boundaries across multiple domains. Our global teams offer various learning opportunities and varied career pathways for those driven to achieve exceptional results through collective effort.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $256000 - $278000 (USD) + 20% bonus target
Learn more about benefits at Google.
In this role, you will join a co-design team within DeepMind’s GenAI Systems, operating across Google’s vertically integrated stack. In this role, you will bring expertise spanning hardware, including architecture, logic design, design verification, and physical design software, such as compilation, performance optimization, libraries, operating systems, and kernels, and algorithms, covering ML model design, optimization methods, numerics, and sparsity. In these fields, you will conduct cutting-edge research while delivering production-quality hardware and software products.
Artificial intelligence will be one of humanity’s most transformative inventions. At Google DeepMind, we are a pioneering AI lab with exceptional interdisciplinary teams focused on advancing AI development to solve complex global challenges and accelerate high-quality product innovation for billions of users. We use our technologies for widespread public benefit and scientific discovery, ensuring safety and ethics are always our highest priority.We are pushing the boundaries across multiple domains. Our global teams offer various learning opportunities and varied career pathways for those driven to achieve exceptional results through collective effort.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $256000 - $278000 (USD) + 20% bonus target
Learn more about benefits at Google.
- Architect, design, and implement hardware for novel systolic array accelerators.
- Own subsystems up to the entire accelerator, carry the implementation of those subsystems from requirements through design sketches, implementation, timing closure, through tapeout, and into bringup and application mapping.
- Collaborate with application, algorithm, and performance-tuning experts to codesign solutions for the best efficiency, performance, and programmability.
- Write code for accelerators to meet up with production requirements at the system, library, and application levels.
- Bring a generalist approach to computer systems beyond specific hardware-related skills, interfacing with colleagues in a wide span of disciplines.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 10 years of experience with leading multiple design domains (Design For Test, Design Verification and Physical Design).
- 5 years of experience with logic design, computer architecture, and circuit theory.
- 5 years of experience in power or performance modeling or system performance analysis.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- 2 year of experience in linux kernel programming.
- Experience with processor core architectures (such as ARM, x86, RISC-V, etc.) and IPs commonly used in SoC designs.