Staff Solution Architect-TC29099

• Architect rack- and pod-scale heterogeneous-compute platforms across CPU, GPU, and DPU — host-to-accelerator interconnect design (PCIe Gen5/6), GPU fabric topology (NVLink / NVSwitch), data-center fabric architecture (leaf-spine and multi-tier), NUMA-aware platform balance, RDMA data-path engineering, and workload-driven DPU placement.
• Engage architecture ahead of configuration lock for every massive-scale AI/GPU cluster; drive end-to-end low-latency fabric design with measured targets.
• Hands-on validation and benchmarking of Nvidia GPU cluster platforms — and future AMD GPU solutions — in partnership with the Solution Engineering team; own the test plan, run the workloads, and interpret results against Nvidia NCP (Cloud Partner) reference architecture and Nvidia Blueprints (AIDP, VSS — Video Search and Summarization — and adjacent blueprints); land Architecture in the room before BOM lock.
• Integrate software-defined and disaggregated storage (VAST DASE, VAST Data Engine) into GPU-accelerated clusters — KV-cache tiering, zero-copy data paths, and SDS validation as a repeatable, Supermicro-owned cycle.
• Co-author joint reference architectures with VAST and NVIDIA (Vast Ebox/C+D Appliance, AIDP / CNode-X); lead architecture for strategic accounts from discovery through PoC, design-win, and on through deployment.
• Productize DCBBS into sellable solutions; define reference configurations with regional PM, and gear up regional PM teams with the tools, reference materials, and architectural knowledge they need to promote DCBBS in-region — the working model is enablement, not hand-off.
• Maintain partnerships with NVIDIA, AMD, Intel, and Marvell; track their roadmaps 12–18 months ahead and leverage them in our designs.
• Produce whitepapers, reference architectures, and field enablement; coordinate across PM, BD, Sales, FAE, Engineering, and Marketing; mentor across divisions.

Qualifications:

• 8–12 years related experience, including 5+ in customer-facing solution architecture for compute, storage, or networking at scale.
• Deep CPU/GPU/DPU integration knowledge — PCIe topology, NVLink/NVSwitch, NUMA, RDMA, high-speed Ethernet/InfiniBand.
• Hands-on with NVIDIA HGX/MGX and GB200/GB300-class platforms; Spectrum-X or InfiniBand fabric design; CUDA-stack awareness.
• Working knowledge of high-performance and software-defined storage (parallel/object SDS) and its integration into GPU-accelerated environments.
• Proven ability to translate AI training/inference, Enterprise AI/AIDP, Video AI, and edge workloads into validated rack-scale designs with quantified performance and TCO.
• Hands-on AI cluster benchmarking and performance profiling — design and execute workload-driven test plans against vendor reference architectures and blueprints (e.g., Nvidia NCP, AIDP, VSS), profile GPU/CPU/interconnect/storage bottlenecks with standard tooling (NCCL/RCCL, MLPerf, nsys/nvprof, PCIe and fabric telemetry), and translate results into platform and BOM decisions/knowledge.
• Hands-on with Kubernetes, container orchestration, virtualization, and cloud-native network functions — sufficient to support 5G core projects end-to-end, including control- and user-plane separation. Video AI and sovereign-edge exposure, along with Tier-1 telco, hyperscaler, or neocloud experience, strongly preferred.
• BS in EE/CE/ME, CS, or related; MS or MBA preferred. Domestic and international travel 25–40%.