Staff Systems Engineer

Description

The Skyworks RMI-Timing Systems Engineering Team is an elite group of system design engineers focused on developing products and solutions for attractive market opportunities in the form of reference designs, derivative ICs with embedded firmware, and packages. The systems engineering team provides system and application-level expertise to the IC design, software, firmware, validation and application engineering teams. System design engineers have a deep understanding of all aspects of timing system development including product definition, platform design, and validation planning.

Responsibilities

PRIMARY RESPONSIBILITY: Designs, defines and implements complex system requirements. Determines system specifications, input/output processes and working parameters for hardware/software compatibility. Coordinates design of subsystems and integration of total system. Identifies, analyzes and resolves program support deficiencies. Develops and recommends corrective actions.

• System and platform design leveraging Skyworks Timing portfolio.
• Lead definition, verification, and validation of timing products.
• Develop FPGA IP for emulation, in-house testing, and reference designs.
• Work with cross-functional teams to take the design into production.
• Collaborate with the silicon design team to develop verification/validation tests for silicon under development.
• Collaborate with marketing and application teams to define next generation of products.
• Collaborate with our Software teams to develop innovative FPGA IPs in our PTP reference designs
• Collaborate with cross-functional teams to take a product from definition to production and eventually to end-of-life.

Required Experience and Skills

• MSEE in EE with 6+ years of experience or BSEE with 8+ years of experience with systems design preferably in communications or high performance mixed-signal products.
• Experience with system-level simulation tools such as MATLAB.
• Experience with System Verilog, UVM and RNM.
• Experience with FPGA or an ASIC digital design flow.
• Experience with lab equipment such as spectrum analyzers, phase noise analyzers etc.
• Good understanding of phase locked loops, control theory and EM theory; knowledge in communication theory, RF design and signal processing.
• Results oriented and practical minded.
  
  

Desired Experience and Skills

• Familiarity with IEEE-1588 compliant networks is a plus.
• Prior experience with PLL design, validation is a plus.
• Prior experience with timing product development is a plus.