System Validation Engineer (New Grad)

The Role:

As a RISC-V System Validation Engineer in the CoreIP team, you will be responsible for performing root cause analysis of SiFive cores on silicon. You will work closely with the System Software team to help in reproducing the issues reported by customers and facilitate internal debugging bridging the communication between HW and Software teams.

Responsibilities
*Owns system-level root cause analysis across processor, SoC, bootloaders, Linux kernel, board, and tools
*Drives failure triage with customer silicon and decomposes ambiguous failures into testable hypotheses and structured debug plans
*Work closely with the FPGA team to reproduce the failure in the emulation environment.