SystemC Modeling Designer

1. Responsible for SystemC platform modeling and simulation of bus system in including functional modeling and performance analysis.
2. Develop reusable and extensible SystemC models according to system specifications to support system architecture planning and verification.
3. Participate in behavioral and high-level abstraction (TLM, Transaction-Level Modeling) model design and verification for SoC (System-on-Chip) and IPs.
4. Collaborate with hardware, software, and verification teams for flow integration, co-debugging, and problem analysis.
5. Prepare technical documents and model descriptions to support design, verification, and customer applications.

Requirements

1. Proficiency in SystemC/C++ programming and object-oriented design concepts.
2. Experience with high-level modeling of chips or system platforms is preferred.
3. Basic knowledge in SoC architecture and bus protocols (e.g., AXI, AHB, CHI) is a plus.
4. Familiarity with Linux/Unix development environments.
5. Good cross-team communication and problem-solving skills.

Preferred Qualifications:
1. Experience in TLM-2.0, hardware/software co-simulation, or virtual platform development.
2. Familiarity with Verilog or other hardware description languages.
3. Experience with Python/Perl/Shell scripting for automation is a plus.
4. Experience in collaborating with international teams.
Education: Master's Degree