UVM/ SystemVerilog Design Verification Engineer

Goleta, CA Contract Job Description: The project relates to the design and verification of a custom controller for analog components. The controller has interfaces such as SPI, Ethernet and AXI to driven the internal components and send data. Responsibilities As a UVM/ SystemVerilog Design Verification Engineer, you will own functional verification for a custom controller. You will develop functional verification infrastructure to ensure functional correctness of a design as well as improve …