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At Kandou , we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable…
Evaluates and integrates new hardware/firmware components for Infinidat’s enterprise storage platforms, debugging complex issues and supporting cross-functional teams in R&D, QA, and IT.
Designs, tests, and verifies MW-scale power-electronics converters for renewable-energy grids, using simulation and lab work to ensure performance and efficiency.
Installs and maintains server hardware for lab equipment, collaborating with a team to ensure smooth operations and adapt to varying technical needs.
Leads end-to-end hardware engineering for AI sports cameras, overseeing optics, electronics, firmware, and manufacturing to deliver scalable, reliable products globally. Bridges technical, product, and business teams to align roadmaps, budgets, and cross-functional execution.
Who we are Sphere Defense is a fully funded technology startup with the mission of providing allied countries with sovereign, effective and seamless autonomous countermeasures to neutralize todays’ and tomorrow’s…
Hardware Engineer (L2/3) supporting critical infrastructure systems through hardware diagnostics, maintenance, and repair across diverse enterprise and legacy platforms in a critical operational environment.
At UVeye, we're on a mission to redefine vehicle safety and reliability on a global scale. Founded in 2016, we pioneered the world's first fully automated suite of AI-powered vehicle inspection systems,…
The Physical Design Engineer will manage the end-to-end physical implementation of System-on-Chips (SoCs) for drone autonomy technology, covering tasks from synthesis to GDSII sign-off. The role involves utilizing industry-standard EDA tools to ensure timing closure, power efficiency, and physical verification.
The SMTS Silicon Design Engineer will develop host controller IP for high-speed I/O technologies using Verilog HDL. This role involves designing, verifying, and mentoring junior engineers to support next-generation high-performance computing and AI products.
In September 2024, Morgan Scientific Incorporated (MSI) joined the Vitalograph group of companies as a wholly owned subsidiary. Vitalograph – a global leader in respiratory diagnostics – has had a long and enduring…
FACNAV er et toppmoderne Battlefield Management System. Vi lager kart-baserte kommando- og kontrollverktøy for operative militære miljøer. Våre løsninger skal gi rett informasjon til rett tid, slik at man kan ta gode…
The Senior SoC Design Verification Engineer leads the verification of complex SoC features and subsystems using SystemVerilog and UVM. The role involves driving verification methodology, ensuring silicon sign-off, and mentoring engineering teams.
DFX RTL design engineer on AMD's Client SOC DFX team, planning and implementing DFX features (JTAG, Scan, Boundary Scan, Debug) and low-power UPF support for next-gen microprocessors using Verilog/SystemVerilog/VHDL and scripting languages.
The Silicon Design Staff Engineer will lead verification efforts for PCIe subsystem IP, developing testbench infrastructure and verification plans. The role requires extensive experience in ASIC design verification and proficiency in UVM and SystemVerilog to support high-performance interconnect development.
About Ethernovia, Inc. Ethernovia is developing the future of Ethernet-based networks to realize the full potential of software-defined and autonomous vehicles, robotics and other intelligent machines. Founded in 2018,…
The Research Engineer will develop and implement complex algorithms on FPGAs and low-level software in C/C++ for real-time and high-performance computing applications in remote sensing and surveillance. The role involves collaborating with multidisciplinary teams to optimize sensor processing and hardware performance.
The Staff Analog Design Engineer will own the transistor-level design of high-speed SerDes transmit and receive datapath blocks for AI inference accelerators. This role involves the full design lifecycle from specification and simulation to silicon characterization using tools like Cadence Virtuoso, MATLAB, and Python.
Staff Analog Design Engineer responsible for transistor-level design of clocking subsystems in high-speed SerDes on IO chiplets, including PLL, DLL, phase interpolator, clock distribution, and CDR loop. Work spans design, simulation, verification, and silicon characterization using tools like Cadence Virtuoso and Spectre.
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