Point your AI agent at freehire and let it find you a job. A CLI and an MCP server over the whole job API — no browser.
The Physical Design Engineer will manage the end-to-end physical implementation of System-on-Chips (SoCs) for drone autonomy technology, covering tasks from synthesis to GDSII sign-off. The role involves utilizing industry-standard EDA tools to ensure timing closure, power efficiency, and physical verification.
The SMTS Silicon Design Engineer will develop host controller IP for high-speed I/O technologies using Verilog HDL. This role involves designing, verifying, and mentoring junior engineers to support next-generation high-performance computing and AI products.
In September 2024, Morgan Scientific Incorporated (MSI) joined the Vitalograph group of companies as a wholly owned subsidiary. Vitalograph – a global leader in respiratory diagnostics – has had a long and enduring…
FACNAV er et toppmoderne Battlefield Management System. Vi lager kart-baserte kommando- og kontrollverktøy for operative militære miljøer. Våre løsninger skal gi rett informasjon til rett tid, slik at man kan ta gode…
The Senior SoC Design Verification Engineer leads the verification of complex SoC features and subsystems using SystemVerilog and UVM. The role involves driving verification methodology, ensuring silicon sign-off, and mentoring engineering teams.
DFX RTL design engineer on AMD's Client SOC DFX team, planning and implementing DFX features (JTAG, Scan, Boundary Scan, Debug) and low-power UPF support for next-gen microprocessors using Verilog/SystemVerilog/VHDL and scripting languages.
The Silicon Design Staff Engineer will lead verification efforts for PCIe subsystem IP, developing testbench infrastructure and verification plans. The role requires extensive experience in ASIC design verification and proficiency in UVM and SystemVerilog to support high-performance interconnect development.
About Ethernovia, Inc. Ethernovia is developing the future of Ethernet-based networks to realize the full potential of software-defined and autonomous vehicles, robotics and other intelligent machines. Founded in 2018,…
The Research Engineer will develop and implement complex algorithms on FPGAs and low-level software in C/C++ for real-time and high-performance computing applications in remote sensing and surveillance. The role involves collaborating with multidisciplinary teams to optimize sensor processing and hardware performance.
The Staff Analog Design Engineer will own the transistor-level design of high-speed SerDes transmit and receive datapath blocks for AI inference accelerators. This role involves the full design lifecycle from specification and simulation to silicon characterization using tools like Cadence Virtuoso, MATLAB, and Python.
Staff Analog Design Engineer responsible for transistor-level design of clocking subsystems in high-speed SerDes on IO chiplets, including PLL, DLL, phase interpolator, clock distribution, and CDR loop. Work spans design, simulation, verification, and silicon characterization using tools like Cadence Virtuoso and Spectre.
Hardware Strategic Sourcing & Manufacturing Partnerships Manager at OpenAI in Singapore, leading strategic engagements with manufacturing partners (JDMs, CMs, ODMs) for AI hardware development, managing the complete manufacturing partner lifecycle from sourcing strategies to long-term partnership management.
Manage hardware cost of goods sold (COGS) and inventory end-to-end at OpenAI, performing forecasting, variance analysis, and collaborating with cross-functional teams to ensure financial data integrity and inform business decisions.
Implement and troubleshoot complex automation systems for diagnostics labs across Europe, traveling 80% of the time to customer sites.
A Senior Mask Design Engineer at NVIDIA designs and develops sophisticated layouts of silicon interposers for GPU products, collaborating with technical leads and teams to ensure product packages meet performance and manufacturing requirements using Cadence tools.
Hardware Engineer Intern at Electrolux in Hangzhou, responsible for electronic circuit design development and participating in home appliance R&D; core technologies include electronic circuit design and analog/digital circuits.
Designs integrated circuits (ICs) for low-power wireless connectivity solutions, focusing on embedded technology for IoT applications in smart home, industrial IoT, and smart cities.
Design and validate power systems for Ring’s IoT doorbells and cameras, ensuring efficiency, safety, and compliance while automating tests and troubleshooting anomalies.
Designs and develops digital hardware components for radar systems, including transmitters, receivers, and signal processing, from functional requirements to product realization and validation. Works closely with multidisciplinary teams on hardware architecture, PCB design, and testing.
Job Description Summary Lead Design & Development, Sizing, Simulation, Testing & Validation, Certification of LV/MV - VSD/ VFD’s. Job Description Roles and Responsibilities LV/MV Drive Engineering – Core Power…
We couldn't check your fit for this role — add a CV to your profile to see it next time.
