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NVIDIA is seeking M.S. or Ph.D. students for a 12-week Hardware Design for Test (DFT) internship. Interns will work on hardware testing architectures, digital design, and silicon debug using tools like Synopsys and Cadence.
NVIDIA offers 12-week hardware engineering internships for students pursuing degrees in electrical or computer engineering. Interns work on projects across system validation, hardware design, mechanical engineering, and silicon solutions using tools like Python, Verilog, and various CAD software.
Develops Python-based simulation models for satellite communication systems and supports design reviews, integration & test, and on-orbit checkout for U.S. Space Force and Intelligence Community space programs.
The Aerospace Corporation is seeking a Senior Communication Systems Engineer to support space-based communication and navigation payloads through design, analysis, and testing. The role involves developing subsystem requirements, performing link budget analyses, and utilizing tools like MATLAB and Python to support national security space programs.
RELOCATION ASSISTANCE: Relocation assistance may be available CLEARANCE REQUIRED FOR START: Yes CLEARANCE TYPE: Top Secret TRAVEL: Yes, 10% of the Time Description At Northrop Grumman, our employees have incredible…
RELOCATION ASSISTANCE: No relocation assistance available CLEARANCE REQUIRED FOR START: Yes CLEARANCE TYPE: Secret TRAVEL: Yes, 10% of the Time Description At Northrop Grumman, our employees have incredible…
Lead RF/digital hardware sustainment for F-35 systems, defining test strategies and resolving complex issues while mentoring teams in a classified defense environment.
The Lead Hardware Engineer will manage and maintain simulation hardware, modeling components, and networked training systems for military units. This role involves leading a team to ensure system readiness, performing troubleshooting, and overseeing hardware lifecycle management.
Design transistor-level mixed-signal IC circuits (high-speed data converters, RF DACs/ADCs, SerDes PHYs) in advanced FinFET processes using Cadence schematic capture, SPICE simulation, and MATLAB for behavioral modeling.
The Senior FPGA Hardware Engineer will own the full development lifecycle of FPGA IP modules, including architecture, implementation, and verification for real-time simulation hardware. The role involves collaborating with software teams on API integration and utilizing tools like Quartus Prime, Python, and VHDL/Verilog.
Hardware Reliability Engineer developing and executing reliability strategies (FMEA, FTA, HALT, Weibull analysis) for opto-mechanical, electrical, and electro-optical hardware on Amazon's LEO satellite OISL systems.
Quantum Hardware Engineer at Amazon's Center for Quantum Computing building and maintaining experimental quantum hardware, focusing on automated measurement sequences, scientific instrumentation, and system integration in a lab environment.
Designs and owns hardware payload systems for Amazon’s Leo satellite network, focusing on phased arrays for high-bandwidth, affordable connectivity. Works across PCB design, high-speed digital circuits, and test automation while collaborating with cross-functional teams.
Design, develop, and implement FPGA-based digital networking solutions for Amazon's LEO satellite broadband system using Verilog HDL, Versal ACAP, and IGLOO2 platforms through the full uArchitecture-to-silicon-validation lifecycle.
Senior Hardware Engineer designing phased array antenna electronics for Amazon's LEO satellite constellation, owning PCBA development from concept through production, including schematic capture, PCB layout, high-speed digital circuitry design, and manufacturing test.
Hardware Engineer designing phased array antenna PCBA systems for Amazon's LEO satellite broadband constellation, covering schematic capture, PCB layout, RF/high-speed digital circuitry, board bring-up, and production transition.
Amazon LEO is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world. As a…
Design and optimize antenna systems, RF circuitry, and PCB layouts for Amazon's LEO satellite broadband constellation, supporting the full hardware design lifecycle from concept through production.
Job Description Summary As the Power Electronics Engineer you will be responsible for leading and performing Low Voltage and Medium Voltage power electronics and electrical design tasks on Drive System projects. This…
Principal FPGA Design Engineer at Microchip's Chandler Design Center developing and validating FPGA-based platforms for next-gen USB and Ethernet PHY products using Verilog/SystemVerilog RTL design, Vivado, and lab debug equipment.
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