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Physical Design Engineer- Staff to Sr. Staff
Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: QCT’s NSP Physical Design Team is actively seeking a highly experienced Clock Physical Design…
Staff Digital Design Engineer
AMD is hiring a Staff Digital Design Engineer in Edinburgh (hybrid) to implement and optimize DSP algorithms and RTL for 200+Gbps SerDes transceivers, with a focus on power efficiency. Day-to-day work involves SystemVerilog RTL, ASIC front-end flows (lint, synthesis, STA), and collaboration with architecture, hardware, and verification teams.
Staff Analog Design Engineer
Are you a seasoned Analog Design Engineer with a passion for cutting-edge technology in power management? We're seeking a Staff Analog Design Engineer to join our PMIC team in Istanbul. This is a full-time, permanent…
Staff Physical Design Engineer: CPU Implementation & Flow Automation
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive…
Sr. Staff CAD- ASIC Design Verification Agentic Workflow
About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative…
ASIC Digital Design, Staff Engineer - 18954
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis…
Sr. Staff Physical Design Engineer
Lightmatter is leading the revolution in AI data center infrastructure, enabling the next giant leaps in human progress. The company invented the world’s first 3D-stacked photonics engine, Passage™, capable of…
Staff Product Manager, Hardware
Lead the strategy and execution of Oura’s next-generation wearable hardware, from concept to launch, collaborating with engineering, design, and science teams to deliver health-focused smart rings.
Staff Hardware Design Engineer – SoC / NoC
In Cyclad we work with top international IT companies in order to boost their potential in delivering outstanding, cutting edge technologies that shape the world of the future. Currently, w e are looking for an…
ASIC Digital Design, Staff Engineer - 18900
We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design,…
ASIC Digital Design, Staff Engineer - 18871
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis…
Physical Design Engineer, Staff
Company: Qualcomm Canada ULC Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable…
Electronics Engineer Senior Staff (Level 5)
Standard Job Description Space is a critical domain, connecting our technologies, our security and our humanity. While others view space as a destination, we see it as a realm of possibilities, where we can do more —…
Senior Staff FPGA Engineer
Leads FPGA architecture, design, implementation, and verification for space-based satellite communication hardware at the HDL level, working with radiation-tolerant Xilinx/Microsemi devices, mentoring junior engineers, and presenting design reviews to customers and executives.
Sr. Staff Engineer, CPU (Front-End) Verification
Design verification engineer focused on unit-level verification of Tenstorrent's RISC-V CPU front end (instruction fetch, branch prediction, fetch control). Day to day involves building UVM testbenches, generating constrained-random and directed stimulus, developing C++ reference models, and driving coverage closure using SystemVerilog, UVM, C++, and tools like Verilator.

