Tech jobs

ASIC Digital Design, Sr Staff Engineer - 18400

AI Cloud Ethernet Firmware PCIe +2 skills

Senior Staff Interface IP Verification Engineer (Pre-Silicon- PCIe/CXL/DDR/Ethernet) We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered…

3 months ago

ASIC Digital Design, Staff Engineer - 18409

AI Automation Bash Ethernet PCIe +6 skills

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis…

3 months ago

ASIC Digital Design, Sr Staff Engineer - 18410

AI Automation Bash Ethernet PCIe +6 skills

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis…

ASIC Digital Design, Staff Engineer - 18421

ADAS AI Automation Iso 26262 Iso 9001 +5 skills

Staff FuSa Engineer We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation…

Houston Community College

4 months ago

Hardware/Software Technician (Part-time) - Southwest College Staff Pool

Open 62d Part-timeStaff

SUMMARY Install and repair personal computer hardware. ESSENTIAL DUTIES AND RESPONSIBILITIES include the following. Other duties may be assigned. Install, modify, troubleshoot and repair personal computer hardware and…

DZYNE Technologies

Open 62d North AmericaFull-timeStaff

Staff Electronics Engineer, Effectors

Altium CAD Firmware Itar Microcontrollers +1 skills

Irvine, CA

About DZYNE DZYNE Technologies is leading the future of autonomous defense. Based in Irvine, California, we develop and manufacture advanced airborne and ground-based defense solutions deployed in over 50 countries.…

160K – 223K $

Open 62d APACStaff H-1B sponsor history

Sr. Staff Engineer, ASIC Design

India

Bengaluru

A senior ASIC design engineer who designs, verifies, brings up, and debugs digital subsystems in electro-optical SoCs for Ayar Labs' co-packaged optics that move data for AI systems. Day to day: RTL in Verilog/SystemVerilog, testbenches, timing constraints and documentation, and Python-driven silicon bring-up.

AI Asic Cadence Virtuoso C++ Firmware +5 skills

Open 62d APACStaff H-1B sponsor history

Sr. Staff Engineer, Front-End CAD / Design Automation

India

Bengaluru

Owns and scales the front-end CAD/design automation flows for Ayar Labs' ASIC and SoC teams in Bengaluru: building Python/Tcl/Shell/Make tooling for lint, CDC/RDC, regressions, and signoff readiness, supporting Synopsys/Cadence/Siemens EDA deployments, and championing AI-assisted CAD agents and workflows.

AI Asic Assembly Automation Bash +14 skills

Open 62d APACStaff H-1B sponsor history

Sr. Staff Engineer, Hardware Module Integration (Lasers)

Taiwan

Hsinchu

Senior hardware/embedded engineer at Ayar Labs in Hsinchu designing embedded electronics and laser driver architectures (control loops, monitoring firmware) for co-packaged optics that move data for AI systems. Day to day: analog/digital schematic capture and PCB layout support, component integration, hardware bring-up and debugging, and cross-functional work with optics, packaging, and manufactur

AI Embedded Systems Firmware MATLAB Microcontrollers +4 skills

Open 62d North AmericaStaff H-1B sponsor history

Sr. Staff Engineer, ASIC Design

AI Asic Cadence Virtuoso C++ Firmware +5 skills

San Jose, CA

Sr. Staff Engineer designing and debugging digital subsystems for Ayar Labs' electro-optical ASICs (co-packaged optics that move AI data over light). Day to day: writing RTL in Verilog/SystemVerilog, building testbenches, defining timing constraints, and doing silicon bring-up/debug with Python, C/C++, and firmware — on-site in San Jose.

180K – 223K $

Credo Technology Group

4 months ago

Senior Staff Digital Design Engineer

Open 62d On-siteNorth AmericaStaff Salary + equity

AI Analytics Asic C++ Ethernet +8 skills

San Jose Office

Team Credo is looking for a Senior Staff PHY RTL Design Engineer to join our mission to transform connectivity at scale. In this role, you will be responsible for the RTL architecture, design, implementation, and…

Credo Technology Group

4 months ago

Staff Physical Design Engineer

Open 62d On-siteAPACStaff

Singapore

Singapore Office

Credo is seeking a Staff Physical Design Engineer to join our Digital R&D team. In this role, you will lead all aspects of physical design and implementation for SoC designs, collaborating closely with frontend and…

AI Analytics Automation Ethernet PCIe +1 skills

Advanced Micro Devices, Inc

Senior Staff Physical Design Engineer (CORES)

Open 62d EuropeStaff

Ireland

Cork

Senior physical design engineer at AMD leading the physical design team for new CPU core designs in Dublin or Cork, balancing Power, Performance and Area. Day-to-day work spans floorplanning, full-chip timing, DRC/LVS, physical design tools/flows, and building Agentic AI tools to boost team productivity.

Agentic AI AI

ASIC Digital Design, Sr Staff Engineer - 18603

AI Automation Perl Verilog

We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis…

Advanced Micro Devices, Inc

Open 60d North AmericaStaff

Sr. Staff ASIC Design Engineer

AI Automation Bash Cadence Virtuoso FPGA +8 skills

CA, San Jose

At AMD's San Jose office (hybrid), a Sr. Staff ASIC Design Engineer joins the front-end design/integration team for next-generation graphics and compute silicon, focusing on DFT: scan insertion, ATPG pattern generation, gate-level simulation verification, test-cost analysis, and post-silicon bring-up. Tooling includes VCS, TetraMAX/DFTMAX, TestKompress, Perl/Shell, and Verilog RTL.

ASIC Digital Design, Sr Staff Engineer - 18568

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design,…

SystemVerilog Uvm

ASIC Digital Design, Staff Engineer - 18569

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design,…

PCIe SystemVerilog Uvm

ASIC Digital Design, Sr Staff Engineer - 18636

AI Asic Rtl SystemVerilog Uvm

Alternate Job Titles Digital Verification Senior Staff Engineer Mixed-Signal PHY Verification Lead ASIC Verification Sr Staff Engineer RTL/GLS Verification Senior Staff Engineer High-Speed Interface Verification Senior…