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Designs and verifies next-generation FPGAs and ASICs for SpaceX’s Starshield national security programs, using Verilog/SystemVerilog, EDA tools, and collaborating with verification and physical implementation teams.
Designs, tests, and analyzes hardware for Starlink’s ground stations, diagnosing failures and ensuring reliability of satellite internet systems in harsh environments.
Designs and optimizes high-volume consumer hardware for Starlink’s global satellite internet system, from concept through mass production, using CAD, FEA, and manufacturing processes.
Designs and optimizes complex PCBs for SpaceX’s Starshield program, partnering with hardware engineers to build high-reliability boards for space and defense systems.
Designs and tests power conversion systems for Starlink satellites, including DC-DC converters and magnetics, to enable global broadband internet service.
Designs and develops high-voltage power supplies for Traveling Wave Tube Amplifiers used in SpaceX's Starlink satellite internet system, focusing on RF vacuum electronics and space communications hardware.
Designs and implements high-performance ASICs in Verilog/SystemVerilog for SpaceX’s Starlink network, collaborating with cross-functional teams to deliver space-grade silicon for global connectivity.
Designs and implements high-performance ASICs in Verilog/SystemVerilog for SpaceX’s Starlink network, collaborating with cross-functional teams to deliver space-grade chips that enable global broadband connectivity.
Designs and optimizes advanced ASIC/SOC chips for SpaceX's Starlink satellites and ground systems, focusing on physical implementation, timing closure, and verification using EDA tools.
Designs and implements advanced ASIC/SOC chips for SpaceX’s Starlink network, focusing on physical design flows, timing closure, and signoff checks to enable global satellite internet connectivity.
Senior software engineer builds and maintains automated test systems for Starshield satellites, using Python and C++ to validate flight hardware and production processes in a Linux/Windows environment.
Senior Hardware Reliability Engineer at SpaceX’s Starshield program, ensuring satellite hardware reliability through failure analysis, testing, and process improvements for government-focused space systems.
Designs and builds high-reliability electrical systems for Starlink satellites, including antennas, ASICs, and power systems, from concept to on-orbit deployment.
Designs and verifies next-generation ASICs for SpaceX’s Starlink network, ensuring satellite and ground infrastructure connectivity through pre- and post-silicon validation.
Designs and verifies next-generation ASICs for SpaceX’s Starlink network, ensuring chips meet performance and reliability needs for global satellite and ground infrastructure.
Design and build high-reliability electrical hardware for SpaceX’s Starmind satellite constellation, enabling advanced AI compute in orbit with mixed-signal circuits, power systems, and custom compute electronics.
Designs and tests high-reliability power electronics for space-based AI satellites, including DC-DC converters and power distribution systems for orbital compute platforms.
Designs and tests next-generation RF integrated circuits for SpaceX’s Starlink satellite internet network, focusing on high-frequency analog and mixed-signal components in SiGe or CMOS processes.
Designs and routes complex PCBs for Starlink hardware, partnering with engineers to optimize layouts for RF, power, and digital circuits using tools like Mentor Xpedition or Altium.
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this…
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