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Senior Engineer, Hardware
Understand the voltage and power specifications at the location where the equipment is installed Calculate the maximum / minimum capacity of the input power of the equipment Determine the load capacity of the equipment…
Senior FPGA Research Engineer
Overview Barco's Vancouver team is developing FPGA-based sensing and edge AI capabilities for industrial applications. We are looking for a hands-on senior FPGA engineer to lead the sensor acquisition and aggregation…
Sr. Analog Design Engineer
Description Job Description Skyworks is seeking an experienced Analog Design Engineer to join the Defense & Aerospace High-Power RF Solutions (HPRF) product development team. This engineer will lead the design and…
Senior Hardware Engineer Control Electronics (m/f/d)
AVL Software and Functions GmbH offers a job in Germany (DE) as Elec - Senior Hardware Engineer Control Electronics (m/f/d) YOUR RESPONSIBILITIES: Define and develop requirements and system architectures for new and…
Senior Hardware Engineer Control Electronics (m/w/d)
AVL ist das weltweit größte, unabhängige Unternehmen für Entwicklung, Simulation und Testen von Antriebssystemen (Hybrid, Verbrennungsmotor, Getriebe, Elektroantrieb, Batterien, Brennstoffzelle und Regelungstechnik)…
Hardware Tools Engineer
Builds and evolves the language, compiler, and tooling that MatX hardware engineers use daily — chiefly the open-source Bluespec compiler (Haskell) plus Rust-based hardware libraries, simulators, and design/verification flows — so architects, designers, and verification teams on the AI chip can move faster.
Senior SoC Design Verification Engineer
Senior SoC Design Verification Engineer at Quadric, an edge-AI processor startup: architect and build a scratch-built SoC-level UVM verification environment for GPNPU-based SoCs, develop directed/random tests, verify 3rd-party IP (NoC, PCIe/UCIe, DDR), and drive coverage using SystemVerilog/UVM, VCS, Verilog/C co-simulation, assembly, and Python.
Senior Hardware Engineer - Micro-Architect
Senior hardware engineer at Quadric (Burlingame, CA) who owns microarchitecture definition and RTL implementation of their General Purpose Neural Processing Unit in SystemC/SystemVerilog, drives PPA optimization, and carries designs through timing closure to tapeout for an edge-AI processor startup.
Senior Hardware Diagnostics Engineer - Infrastructure
Owns the firmware lifecycle (BIOS, BMC, NIC, GPU, storage) and hardware validation for TensorWave's large-scale AI GPU cloud — qualifying releases, building fleet-scale automated validation and burn-in tooling, and leading root-cause analysis on hardware failures. Core stack: Linux, Python, Redfish/IPMI, AMD platforms.
Senior Softgoods Digital Design Engineer
Senior Class-A surface modeler on 1X's Softgoods team who turns industrial design for the NEO humanoid robot into production-grade digital geometry in Autodesk Alias, translating sketches, clay, and scan data into manufacturable surfaces for soft covers, foams, and elastomers, and carrying them through tooling release to mass production.
Senior FPGA Engineer
Design, implement, and verify mission-critical FPGA firmware for K2 Space's high-power satellites — owning RTL architecture in VHDL/SystemVerilog that controls propulsion, attitude control, RF, and power systems, and validating designs via simulation, bench testing, and hardware-in-the-loop testbeds.
Senior Power Electronics Engineer
Designs some of the highest-power electronics ever flown in space (20-100 kW) for K2 Space's large satellites: prototyping power switching/conversion hardware, qualifying it through environmental testing (vibration, thermal, TVAC), and taking flight hardware from concept to orbit. Core tools: power electronics design, LTspice, C/C++, Python, Matlab.
Senior ASIC Design Verification Engineer
K2 Space is hiring a Senior ASIC Design Verification Engineer to verify the functionality, performance, and robustness of custom silicon for its high-power satellites. Day to day, this means building SystemVerilog/UVM testbenches, writing assertions, running and debugging simulations, driving coverage closure, and managing regressions/CI, plus supporting silicon bring-up.
Senior Hardware Reliability Engineer
Senior Hardware Reliability Engineer at K2 Space in Los Angeles will own reliability requirements, modeling (Weibull, Monte Carlo, PRA), HALT/HASS and accelerated test strategies, and root-cause investigations for high-power satellites moving toward mass production. Requires an engineering B.S. and 5+ years in reliability/hardware testing; pays $140k–$175k plus equity.
Senior ASIC Physical Design Engineer
At K2 Space, a satellite maker, you'd own the full ASIC physical design flow for mixed-signal SoCs that fly on satellites — synthesis, floorplanning, place & route, CTS, STA, timing closure, and sign-off (DRC/LVS, IR drop, EM) through GDSII — using tools like Synopsys ICC2/Fusion Compiler and Cadence Innovus.
Senior FPGA Engineer (TS/SCI)
Design and verify mission-critical FPGA firmware for high-power satellites, implementing real-time control, networking, and RF systems in VHDL/SystemVerilog.
Senior FPGA Prototyping Engineer
Senior FPGA engineer building hardware prototypes and validating next-gen satellite communications ASICs, from FPGA bring-up to first-silicon debug.
Senior RF Hardware Engineer
Designs and develops RF and microwave electronics (UHF through Ka-band) for high-power satellites, owning architecture, PCBA design in Altium, and environmental/TVAC testing of SDR hardware. Requires 5+ years of RF engineering experience plus RF modeling tools (AWR Microwave Office, Keysight ADS) and test equipment like VNAs.
Senior FPGA Engineer (m/w/d) – Direktvermittlung (m/w/d) (Informatiker/in)
Unser Angebot:- Festanstellung in einem wachsenden Unternehmen mit flachen Hierarchien- 40 % Remote-Anteil, freitags immer im Homeoffice- Flexible Arbeitszeiten mit Gleitzeitkonto- Bruttogehalt ab 52.000 € je nach…
Senior Hardware Systems Engineer
Senior Hardware Systems Engineer on Microsoft's Azure Cloud Hardware and Infrastructure Engineering (CHIE) team in Redmond, WA: designs and executes system validation plans, builds test/debug frameworks and automation, and debugs server subsystems (CPU/GPU) for Azure cloud hardware. Works with Python/PowerShell, C/C++, Windows/Linux, and PCIe/firmware-level debug tools.