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Palomar Products Inc.
8 views 6 days ago

Principal Hardware Engineer (onsite)

New North AmericaContractPrincipal
United States
Rancho Santa Margarita, CA

Principal Hardware Engineer Department: Engineering Reports to Title: VP of Engineering and Quality Palomar Products Palomar Products is a wholly owned subsidiary of TransDigm Group specializing in secure…

As9100 Ethernet Firmware I2c Itar +3 skills
175K – 195K $
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Terran Orbital
29 views 6 days ago

Principal FPGA Design Engineer

New North AmericaFull-timePrincipal 7 questions
United States
Irvine, CA

Join a team where your impact reaches beyond the stars! At Terran Orbital, you’re not just part of the system – you’re a vital force propelling our mission forward. As trailblazers in satellite manufacturing and…

Bash C++ Embedded Software Ethernet FPGA +11 skills
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Astera Labs
111 views 6 days ago

Principal Digital Design Engineer (AI Fabric)

Open 144d North AmericaPrincipal 4 questions H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
United States
San Jose, CA

Principal Digital Design Engineer at Astera Labs designing high-performance connectivity solutions for AI infrastructure, using RTL, synthesis, and advanced CMOS nodes.

AI Automation CAD Cmos Ethernet +6 skills
185K – 230K $
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Astera Labs
94 views 6 days ago

Principal Physical Design Engineer, STA

Open 144d On-siteNorth AmericaPrincipal 3 questions H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
United States
San Jose, California

Principal Physical Design Engineer (STA) at Astera Labs designs and optimizes timing for high-performance connectivity ASICs used in AI infrastructure, leveraging advanced EDA tools and TSMC 7nm processes.

AI Automation Cloud Ethernet Networking +8 skills
209K – 250K $
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Astera Labs
89 views 6 days ago

Senior Principal Digital Design Engineer

Open 144d North AmericaPrincipal 4 questions H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
United States
San Jose, CA

Senior Principal Digital Design Engineer at Astera Labs in San Jose, CA, leading architecture and RTL implementation for AI connectivity chips using PCIe, CXL, UALink, Ethernet, and DDR protocols.

AI Automation CAD Cmos Ethernet +4 skills
205K – 255K $
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Astera Labs
20 views 6 days ago

Staff / Principal ASIC Design Engineer

Open 109d MENAPrincipal 3 questions H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
Israel
Tel Aviv-Yafo, Tel Aviv District

Designs and implements high-performance digital ASIC blocks for AI infrastructure connectivity chips, from RTL to backend, using Verilog/SystemVerilog and EDA tools.

AI Asic Automation Ethernet PCIe +5 skills
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Astera Labs
69 views 6 days ago

Senior Principal ASIC Design Engineer

Open 92d On-siteEuropePrincipal No extra questions H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
Germany

Lead ASIC design for high-speed Ethernet and AI interconnect fabrics, defining architecture and RTL for controllers, NICs, and packet processing pipelines to enable rack-scale AI infrastructure.

AI Asic Ethernet Firmware HPC +7 skills
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Astera Labs
63 views 6 days ago

Principal Hardware Validation Engineer

Open 91d North AmericaPrincipal 3 questions H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
United States
San Jose, California

Designs and implements RTL for high-speed interconnect silicon (PCIe, CXL, Ethernet) that powers AI infrastructure, shepherding blocks from spec to tapeout.

AI Ethernet I2c Oscilloscope PCIe +4 skills
133K – 185K $
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Astera Labs
37 views 6 days ago

Principal Hardware Applications Engineer – PCIe Switches (Scorpio)

Open 77d North AmericaPrincipal 3 questions H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
Canada
Vancouver, British Columbia

Principal applications engineer at Astera Labs (NASDAQ: ALAB) serving as the technical lead for Scorpio Smart Fabric Switches, guiding hyperscalers and AI system builders through design-in, bring-up, and post-silicon debug of PCIe Gen 6/7 and UALink platforms. Deep high-speed serial interface expertise and lab validation skills required; CAD 165k–210k.

AI Automation Bash Cloud Ethernet +7 skills
165K – 210K CAD
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Astera Labs
68 views 6 days ago

Principal Analog Mixed-Signal Design Engineer

Open 52d North AmericaPrincipal 3 questions H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
San Jose, California

Hands-on principal-level analog IC designer at Astera Labs who architects high-speed analog/mixed-signal circuits (PLLs, SerDes, ADCs/DACs, clocking) for AI infrastructure connectivity silicon in advanced FinFET nodes, owning designs from spec through silicon bring-up while setting methodology and mentoring the analog team in San Jose.

AI Cadence Virtuoso Cmos Ethernet PCIe +2 skills
207K – 230K $
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Astera Labs
15 views 6 days ago

Principal/ Sr Principal Digital Design Engineer

Open 49d APACPrincipal No extra questions H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
Taiwan
Taipei

Senior digital design engineer at Astera Labs owning complex digital blocks for AI connectivity silicon — from micro-architecture and RTL implementation through timing closure, DFT, verification support, and silicon bring-up — targeting PCIe Gen 6/7, CXL, UALink, Ethernet, and DDR protocols on sub-7nm nodes using Cadence/Synopsys flows.

AI Automation CAD Cmos Ethernet +4 skills
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Astera Labs
46 views 6 days ago

Principal/ Sr.Principal Digital Design Engineer

Open 49d North AmericaPrincipal No extra questions H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
United States
San Jose, California

Architects and implements complex digital blocks for Astera Labs' AI connectivity silicon, owning designs from micro-architecture and RTL through timing closure, DFT, verification, and post-silicon bring-up for protocols like PCIe Gen 6/7, CXL, UALink, UCIe, Ethernet, and DDR, using Cadence/Synopsys flows on advanced CMOS nodes.

AI Automation CAD Cmos Ethernet +4 skills
185K – 230K $
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Astera Labs
21 views 6 days ago

Principal Analog Mixed-Signal Design Engineer

Open 45d APACPrincipal 3 questions H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
Vietnam
Ho Chi Minh City

Designs high-speed analog/mixed-signal circuit blocks (PLLs, CDRs, TX drivers, RX front-ends, equalizers) for multi-gigabit wireline transceiver IPs at advanced FinFET nodes, from transistor-level design and simulation through silicon bring-up. Primary tools include Cadence Virtuoso, Spectre, MATLAB, and Python.

AI Ethernet Firmware MATLAB PCIe +1 skills
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Astera Labs
2 views 6 days ago

Principal Digital Design Engineer

Open 28d North AmericaPrincipal 3 questions H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
United States
San Jose, California

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the…

AI Cmos Ethernet Express.js Firmware +4 skills
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Astera Labs
32 views 6 days ago

Principal Hardware NPI Program Manager

Open 28d North AmericaContractPrincipal 3 questions H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
United States
San Jose, California

Lead hardware NPI programs at Astera Labs from design release through PCBA builds, validation, manufacturing readiness, and launch of connectivity hardware for rack-scale AI infrastructure. The role is cross-functional program management across hardware, systems, supply chain, quality, and contract manufacturers, grounded in PCB/PCBA expertise.

AI Assembly Automation Data Pipelines Design for Manufacturing (DFM) +8 skills
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Astera Labs
26 views 6 days ago

Principal Physical Design Engineer

Open 22d APACPrincipal 3 questions H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
India
Ahmedabad, Gujarat

Astera Labs is hiring a Principal Physical Design Engineer in Ahmedabad to own complex SoC/silicon backend design from synthesis through GDSII (place-and-route, CTS, STA, physical verification) at 16nm-and-below nodes, using Cadence/Synopsys flows for its AI connectivity chips. Requires 8+ years' experience plus Verilog/SystemVerilog, DFT, and Python/Perl scripting.

AI Cloud Ethernet Networking PCIe +3 skills
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Astera Labs
28 views 6 days ago

Principal Mixed Analog Design Engineer

Open 21d North AmericaPrincipal 3 questions H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
United States
Irvine, California

Principal Analog Design Engineer who architects and designs high-speed analog/mixed-signal circuits (PLLs, SerDes building blocks, ADCs/DACs, references, clocking) for Astera Labs' AI connectivity silicon, owning designs from spec through layout and silicon bring-up in advanced FinFET nodes, using Cadence Virtuoso/Spectre and mentoring the analog team.

AI Cadence Virtuoso Cmos Ethernet PCIe +2 skills
170K – 210K $
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Astera Labs
18 views 6 days ago

Principal Physical Design Engineer

Open 20d APACPrincipal 3 questions H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.Canada LMIA employer — This employer was issued a positive Labour Market Impact Assessment by Employment and Social Development Canada in the last four quarters, through the High Wage, Global Talent or Permanent Resident streams. The approval belongs to the employer and is not a commitment to sponsor this role.
Singapore

Physical design engineer at Astera Labs implementing next-generation high-speed transceiver IPs at TSMC 3nm and advanced nodes: floorplanning, placement, CTS, routing, EM/IR and congestion analysis, ECOs, and DRC/LVS/ERC signoff using ICC2, Innovus, Voltus, RedHawk, and Calibre, plus Tcl/Python/Perl flow automation.

AI Automation Ethernet PCIe Perl +3 skills
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SiTime Corporation
27 views 6 days ago

Principal Analog Mixed-Signal Design Engineer

New North AmericaPrincipal 7 questions Licensed NL sponsor — This employer appears on the IND public register of recognised sponsors for work and highly skilled migrants. The recognition belongs to the employer and is not a commitment to sponsor this role.H-1B sponsor history — This employer has had H-1B petitions approved by USCIS in the last five fiscal years, per the USCIS H-1B Employer Data Hub. The approval belongs to the employer and is not a commitment to sponsor this role.
United States
California, Santa Clara

Principal engineer leading analog/mixed-signal IC design at SiTime: owns top-level schematics and simulations, architects and designs circuits such as PLLs, oscillators, and ADC/DACs in CMOS/BiCMOS, supervises block designers and layout, and drives silicon through validation to high-volume production using Cadence EDA tools.

AI CAD Cadence Virtuoso Cmos IoT
148K – 204K $
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BAE Systems
23 views 6 days ago

Senior/Principal Hardware Engineer

New UKPrincipal Licensed UK sponsor — This employer appears on the GOV.UK register of licensed sponsors for the Skilled Worker and related work routes. The licence belongs to the employer and is not a commitment to sponsor this role.
United Kingdom

Senior/Principal Hardware Engineer at BAE Systems in Rochester (onsite) designing digital/analogue electronics for safety-critical aerospace products such as helmet-mounted displays, mission computers, and flight controls, through the full development lifecycle (e.g. DO-254) using Mentor Graphics, Simetrix, and LTspice; circa £60,000 per year.

60K – 60K £