Point your AI agent at freehire and let it find you a job. A CLI and an MCP server over the whole job API — no browser.
About the Team Like every team at OpenAI, the Marketing team contributes to our broader mission of ensuring responsible and widespread adoption of artificial intelligence With that aim in mind, we are responsible for…
Performs high-precision electrical rework, assembly, and modifications on R&D prototypes and test fixtures for Apple’s hardware products, managing lab operations, equipment, and cross-functional collaboration.
The Principal Hardware Robotics Engineer will lead the strategy and technical development of robotics automation systems for Google's data centers, including AMRs and robotic arms. The role involves defining the robotics roadmap and integrating AI-driven solutions to optimize hardware deployment and maintenance.
RF Design Engineer developing front-end RF signal-chain circuits, low-phase-noise oscillators, and RF digitizer assemblies for space vehicle communication systems, using EDA/EM tools and lab measurement equipment.
Lightmatter is leading the revolution in AI data center infrastructure, enabling the next giant leaps in human progress. The company invented the world’s first 3D-stacked photonics engine, Passage™, capable of…
Technical Program Manager driving complex, multi-team robotics hardware and software programs, coordinating across engineering teams using Agile methodologies to deliver integrated robotic systems.
Lead the vision, strategy, and execution of hardware quality across WHOOP's global wearable product ecosystem — spanning product development, manufacturing, supplier management, and field performance.
Staff Electrical Hardware Engineer designs and validates complex PCB boards for cutting-edge automotive systems, including DC/DC converters, high-speed digital signaling, and analog circuits, using Altium and collaborating with overseas manufacturers.
Electrical integration engineer designing and validating high-performance compute solutions for Apple data centers, owning schematic capture, board layout guidance, simulation, bringup, debug, and factory build support.
Leads power integrity analysis for AI connectivity ASICs, ensuring stable power delivery and reliability through IR drop and electromigration sign-off from floorplan to tapeout.
Designs high-speed networking hardware (100G/200G Ethernet switches) for AI clusters, datacenters, and enterprise networks, focusing on PCB layout, signal integrity, FPGA control, and system validation.
Design and implement a high-performance, low-power ASIC accelerator for AI inference in autonomous-driving perception modules using Verilog, SoC IP integration, and timing/power optimization.
Principal Physical Design Engineer (STA) at Astera Labs designs and optimizes timing for high-performance connectivity ASICs used in AI infrastructure, leveraging advanced EDA tools and TSMC 7nm processes.
Principal Physical Design Engineer defines and maintains reusable RTL-to-GDSII flows and automation for SoC tapeouts, integrating Cadence and Synopsys tools to optimize PPA and schedule predictability.
Designs hardware architecture for Google’s wearable products, focusing on ambient/edge computing and on-device AI. Balances performance, power, cost, and form factor while collaborating with silicon vendors and cross-functional teams.
Designs and optimizes ultra-low-latency FPGA hardware for electronic trading systems used by top-tier financial institutions.
FPGA Design Engineer responsible for RTL design, development, and optimization of high-performance, ultra-low latency FPGA compute and networking systems for electronic trading infrastructure, primarily using SystemVerilog/VHDL.
Mission Hardware Engineer providing installation, maintenance, and troubleshooting of information systems, peripherals, VoIP, conferencing systems, and network cabling for a mission-critical government program.
Assembles precision hardware components for aerospace and defense systems, inspects parts, and follows detailed manufacturing procedures in a high-tech facility.
Designs and validates high-speed signal integrity for enterprise SSD hardware, running simulations, lab measurements, and cross-team collaboration in Santa Clara.
We couldn't check your fit for this role — add a CV to your profile to see it next time.