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Lead RTL/silicon design engineer for AMD's Data Accelerator team, designing custom hardware offload engines (encryption, compression, compute offloads) for SOCs powering servers, datacenters, and embedded products.
Design and implement FPGA/ASIC applications using OCaml and Hardcaml (an OCaml RTL library) for RTL design and testing, with some Verilog and C work, at a quantitative trading firm.
Interns collaborate with full-time engineers on FPGA/ASIC hardware projects using OCaml and Hardcaml, from design to validation, with mentorship and exposure to Jane Street’s internal tools.
Designs and deploys ultra-low-latency ASIC hardware, owning physical design flows end-to-end while collaborating with trading, networking, and research teams using tools like Hardcaml.
Procure IT hardware like servers and networking gear for offices and data centers, negotiate with vendors, and manage orders and logistics.
We are looking for an ambitious, fast-learning Hardware Engineering Intern to join our product startup. If you are eager to tackle challenging technical problems and rapidly develop your engineering skills, this role…
Develops and executes test plans for AI-native hardware systems, ensuring reliability, performance, and scalability for OpenAI’s supercomputing platform. Focuses on debugging, high-speed SerDes, and cross-team collaboration.
Hands-on Hardware Test & Integration Engineer maintaining and expanding hardware-in-the-loop test benches for a maritime intelligence sensor platform, integrating COTS and custom hardware, writing occasional automated test scripts, and conducting field validation testing aboard vessels.
Commercial Hardware – Project Manager Rochester NY • Commercial Job Type Full-time Description Join our teams at Morse Sash and Door as a Project Manager/Assistant in our Commercial Hardware Department. The ideal…
Validate and stress-test hardware components for high-performance storage arrays, using tools like oscilloscopes and SERDES to ensure reliability and signal integrity across PCIe, DDR5, and networking interfaces.
Design and optimize FPGA fabric architecture—interconnect, routing, logic elements, memory blocks, and clocking—at Microchip's FPGA Business Unit, using full-custom mixed-signal design, HDLs (Verilog/VHDL), and scripting on advanced process nodes.
Principal engineer designing and optimizing high-speed AI networking infrastructure for Microsoft’s MAIA platform, spanning RDMA, TCP/IP, and AI fabric to enable next-gen AI training and inference at hyperscale.
About the Role We are looking for a skilled and proactive Senior Technical Support Officer with specialist expertise in End User Hardware to join our IT Directorate. This role is essential in ensuring the smooth…
Junior AI SoC Design Verification Engineer at Google, planning and executing verification of custom silicon using SystemVerilog, UVM, and formal methods throughout the full development lifecycle to tape-out.
Are you the electronics expert who loves working on innovative products within a multidisciplinary team? As an Electronics Engineer, you’ll design, test, and optimize electronic systems that form the core of our…
Ben jij dé elektronica-expert die graag werkt aan innovatieve producten binnen een multidisciplinair team? Als Electronics Engineer ontwerp, test en optimaliseer je elektronische systemen die het hart vormen van onze…
Design and optimise FPGA-based systems for low-latency, high-throughput data processing and custom hardware acceleration in a small hardware engineering team focused on performance-critical infrastructure.
Own the full mechanical hardware lifecycle—from CAD design and prototyping through manufacturing, deployment, and field maintenance—for Instawork's wearable robotics capture rig (Instacore) in Bangalore.
The Hardware Design Engineer will develop innovative electronic concepts, design circuits, and manage PCB layouts for high-tech instrumentation. The role involves a mandatory 1-3 year international assignment after an initial training period in Graz.
Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission.…
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