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Principal Physical Design Engineer defines and maintains reusable RTL-to-GDSII flows and automation for SoC tapeouts, integrating Cadence and Synopsys tools to optimize PPA and schedule predictability.
Provides senior technical leadership for the architecture and development of next-generation AI, cloud, and high-performance data center networking platforms, including Ethernet, InfiniBand fabrics, switching systems, and NICs/DPUs.
Principal engineer designing and optimizing high-speed AI networking infrastructure for Microsoft’s MAIA platform, spanning RDMA, TCP/IP, and AI fabric to enable next-gen AI training and inference at hyperscale.
Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission.…
Leads SoC design and RTL development for advanced sensor platforms, defining architecture, integrating subsystems, and driving cross-functional teams from concept to silicon.
The Principal Engineer leads hardware failure analysis and root cause investigations for networking products, mentoring team members and collaborating with cross-functional teams to ensure product quality. The role requires deep expertise in hardware design, high-speed signal integrity, and debugging complex networking hardware.
Owns reliability strategies for next-gen satellites, defining requirements, modeling failure rates, and driving testing to ensure mission success and high-volume production.
RELOCATION ASSISTANCE: Relocation assistance may be available CLEARANCE REQUIRED FOR START: No CLEARANCE TYPE: Secret TRAVEL: Yes, 10% of the Time Description At Northrop Grumman, our employees have incredible…
Designs and optimizes DRAM circuits using CMOS logic and AI-enabled tools, leading layout and simulations to deliver high-performance memory solutions.
Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into…
Are you an experienced Power Electronics Engineer looking for an opportunity to shape next-generation electrification technology whilst developing into a future engineering leader? At Advanced Electric Machines (AEM),…
Principal Digital Design Engineer at Astera Labs designing high-performance AI connectivity silicon, owning RTL implementation through silicon bring-up for PCIe, CXL, and other protocols.
Principal Digital Design Engineer at Astera Labs designing high-performance connectivity solutions for AI infrastructure, using RTL, synthesis, and advanced CMOS nodes.
Senior Principal Digital Design Engineer at Astera Labs in San Jose, CA, leading architecture and RTL implementation for AI connectivity chips using PCIe, CXL, UALink, Ethernet, and DDR protocols.
Designs power integrity and electromigration solutions for high-performance AI chips, ensuring voltage stability and reliability in advanced semiconductor nodes.
Lead ASIC design for high-speed Ethernet and AI interconnect fabrics, defining architecture and RTL for controllers, NICs, and packet processing pipelines to enable rack-scale AI infrastructure.
The Principal Hardware Engineer will lead the hardware team and scale the Sniffspace platform, which uses sensors and robotics to present breath samples for canine cancer detection. The role involves end-to-end ownership of hardware design, reliability, and manufacturing processes using technologies like Raspberry Pi, ESP32, and custom PCBs.
The Principal Digital Hardware Design Lead provides technical and program leadership for advanced hardware development, focusing on architecture, governance, and design reviews. This role requires a hybrid presence in Southampton, UK, with three days per week on-site.
About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI,…
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