Designs high-performance digital blocks for AI infrastructure chips, using Verilog/SystemVerilog and EDA tools to solve data bottlenecks in semiconductor connectivity solutions.
Senior engineer builds and runs test environments to verify high-performance AI connectivity chips using SystemVerilog/UVM, ensuring flawless silicon for next-gen data centers.
Designs and implements top-level physical design for AI-focused semiconductor chips, collaborating with cross-functional teams to meet strict performance, power, and area targets.
Designs and implements advanced semiconductor packages for high-performance AI connectivity chips, collaborating with teams to optimize electrical, thermal, and mechanical performance from concept to production.
Senior/Staff STA Engineer at Astera Labs in Israel designs and signs off timing for high-performance AI connectivity chips, using EDA tools and SDC constraints to meet aggressive data-center targets.
Leads the full lifecycle of ASIC chip development for AI infrastructure, coordinating cross-functional teams to design, fabricate, and validate semiconductor solutions.
Designs power integrity and electromigration checks for AI-focused semiconductor chips, using tools like Ansys RedHawk and Cadence Voltus to ensure reliability in advanced FinFET nodes.
Principal Architect at Astera Labs in Tel Aviv designs high-performance AI connectivity solutions, focusing on PCIe, Ethernet, and advanced interconnect protocols like CXL and UALink.
Designs and implements verification environments for high-performance semiconductor chips in AI infrastructure, using SystemVerilog/UVM to validate digital blocks and subsystems.
Designs and runs tests to validate high-speed semiconductor chips (CXL, PCIe, Ethernet) for AI infrastructure, ensuring reliability and performance in server/storage systems.
Designs and implements high-performance digital ASIC blocks for AI infrastructure connectivity chips, from RTL to backend, using Verilog/SystemVerilog and EDA tools.
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the…
A technical manager role at Astera Labs in Tel Aviv owning RTL design execution for connectivity silicon blocks that power large AI clusters — taking features from microarchitecture through synthesis, timing closure, and tapeout using Verilog/SystemVerilog with PCIe, CXL, and Ethernet interconnect technologies.
Senior firmware engineer at Astera Labs in Tel Aviv developing real-time embedded C firmware for AI connectivity silicon — boot, initialization, link management, and telemetry — from pre-silicon emulation through silicon bring-up, while also extending the COSMOS SDK. Requires 10+ years of embedded firmware experience with strong C and hardware debugging skills.
Senior firmware engineer role at Astera Labs in Tel Aviv developing and debugging PCIe embedded firmware in C for AI connectivity silicon — owning link training, enumeration, and error handling end to end, from pre-silicon emulation through post-silicon bring-up, while also extending the COSMOS SDK.
Astera Labs is hiring a Principal Physical Design CAD Engineer for its new Israel R&D center to build and automate physical design CAD flows (synthesis through P&R, timing, power, signoff) for AI connectivity chips, using Synopsys Fusion Compiler plus Tcl/Python automation and exploring GenAI-based methodologies.
Lead the physical design team at Astera Labs in Tel Aviv, taking complex high-speed mixed-signal and digital SoCs from RTL handoff through tapeout for AI connectivity silicon. Day to day: driving floorplanning, placement, CTS, routing, timing/power/signal-integrity closure with tools like Innovus, ICC2, PrimeTime, and Calibre, while mentoring engineers and managing multi-project delivery.
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