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The era of pervasive AI has arrived. In this era, organizations will use generative AI to unlock hidden value in their data, accelerate processes, reduce costs, drive efficiency and innovation to fundamentally…
Designs and maintains the RTL-to-GDS physical design flow for AI accelerator chips using Cadence tools, scripting, and advanced 3nm+ process rules.
Designs and automates end-to-end manufacturing tests for integrated AI compute racks, validating power, cooling, networking, and firmware at scale.
Build and maintain the cloud infrastructure that powers SambaNova’s AI inferencing service, ensuring high availability, low latency, and scalable performance across regions.
Owns outsourced electronics production for an AI hardware company, managing schedules, costs, quality, and supply chain to deliver servers and racks on time and to spec.
Designs, optimizes, and deploys large language models to run efficiently on SambaNova’s custom RDU hardware, guiding hardware-software co-design and production integration.
Leads end-to-end performance optimization for large-scale LLM inference at SambaNova, focusing on workload capture, benchmarking, and predictive modeling to improve latency, scalability, and hardware planning for enterprise AI deployments.
Principal engineer owning verification for next-gen RDU silicon, developing testbenches with SystemVerilog/UVM/Python to validate AI hardware performance and logic.
Principal RTL engineer owns the microarchitecture and SystemVerilog RTL for a major block of SambaNova’s AI accelerator chip, driving PPA trade-offs, timing closure, and tape-out while collaborating with architects and physical-design teams.
Designs and owns RTL blocks for SambaNova’s AI-accelerating RDU ASICs, shepherding them from spec to silicon bring-up while optimizing for power, performance, and area.
Builds and maintains hardware emulation models for SambaNova’s AI workload accelerator (RDU), enabling pre-silicon software bring-up, performance verification, and verification acceleration. Works with RTL teams to ensure emulation-readiness, owns platform automation, and advises cross-functional teams on emulation strategy.
Designs and validates full-stack AI accelerator systems (boards, racks, clusters) for SambaNova’s RDU platform, balancing performance, power, and cooling while guiding vendors and shepherding systems from architecture to deployment.
Design Verification Engineer builds SystemVerilog/UVM test environments to verify AI chip control, initialization, and state transitions for SambaNova’s RDU chip.
A senior hands-on hardware role integrating SambaNova's AI accelerators into rack-scale systems — racking/stacking network, power, and compute gear, prototyping rack designs, and taking them to mass production and customer datacenter deployments. Core work centers on datacenter equipment (switches, power, fiber/copper networking, air/liquid cooling) and cross-team/vendor coordination.
Lead pre-silicon verification for SambaNova’s AI chips, owning methodology, testbenches, and tape-out readiness, then debug first silicon in the lab.
As a Network Solutions Architect at SambaNova, you design reference architectures for integrating the company’s generative AI platform with customer data centers, support complex networking deployments, troubleshoot performance issues, and provide feedback to engineering on product enhancements.
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