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As a Software Engineer Intern on the AI Compiler team at Tenstorrent, you'll work on designing and implementing APIs, extending model import pipelines, developing compiler passes using MLIR, and optimizing neural network execution on custom AI hardware, guided by a mentor.
Leads AI/ML-driven physical design flows for semiconductor IP, optimizing RTL-to-GDS methodologies to improve performance, power, and area (PPA) and runtime across advanced nodes.
Own synthesis and place-and-route for high-speed CPU chiplets in advanced AI silicon using Synopsys/Cadence tools.
Develops and optimizes high-performance C++ components for training machine learning models on custom silicon, working closely with compiler and kernel teams to scale AI workloads efficiently.
Contribute to the design, analysis, and optimization of a high-performance RISC-V CPU’s load-store unit, collaborating with hardware/software teams and using tools like Gem5. Core technologies include RISC-V, CPU architecture, and performance modeling.
Leads CPU core-level test generator development and verification strategy for high-performance RISC-V CPUs, ensuring validation of ISA and microarchitectural behavior across pre- and post-silicon stages.
Leads a team of Verification Engineers to shape test strategies for AI hardware, validating functionality and performance of AI cores. Core technologies include AI-specific data types, compute patterns, on-chip network validation, UVM, SystemVerilog, and cocotb.
Director leading customer-facing hardware engineering at Tenstorrent, owning technical relationships with strategic customers and FAEs to translate silicon needs into RTL/verification specifications for custom AI silicon programs.
Engineering Program Manager for RISC-V CPU development at Tenstorrent, owning full-lifecycle CPU program delivery from spec through tapeout and post-silicon debug, coordinating across architecture, design, verification, physical design, and DFT teams.
As a Fabric SOC Architect at Tenstorrent, you design high-performance System-on-Chip (SoC) interconnect fabrics, bridging software and silicon to optimize AI, HPC, and general-purpose workloads, focusing on NoC, cache coherency, and memory/IO technologies.
Champion Tenstorrent’s RISC-V CPU and AI accelerator IP to customers, translating complex architecture into wins while gathering market feedback to shape product roadmaps.
Full-chip physical design verification engineer ensuring manufacturable silicon for AI SoCs using DRC/LVS/ERC flows and advanced nodes (7nm–3nm).
Designs next-generation CPU networking architectures for AI/ML workloads, focusing on datacenter and emerging robotics/automotive applications using Ethernet, RDMA, and die-to-die interfaces.
Develops and optimizes AI models (LLMs/vision) for custom hardware, tuning performance and accuracy across software, compiler, and hardware layers.
Designs and implements high-performance CPU and AI/ML chip blocks from synthesis to tapeout, optimizing power, performance, and area using advanced EDA tools and methodologies.
Physical Design Engineer owning Die-to-Die interface implementation from RTL to GDSII for advanced-node chiplet architectures, using full PD flow (synthesis, P&R, CTS, sign-off) with Synopsys/Cadence/Mentor EDA tools and Tcl/Python automation.
Designs and implements high-performance AI SoC partitions from synthesis to tapeout, focusing on timing, power intent, and physical verification using Synopsys tools (Design Compiler, Fusion Compiler, IC Compiler II).
Drive static timing analysis and closure for high-performance RISC-V CPUs and AI SoCs, collaborating with logic, DFT, and physical design teams using STA tools, SDC constraints, and Python/Perl/TCL scripting.
Develop and optimize RISC-V AI/HPC software stacks and agentic systems using C/C++, working at the hardware-software boundary.
Develop high-performance Linux kernel and user-mode drivers for Tenstorrent's AI hardware, focusing on PCIe integration and cross-layer optimization.
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